feat:(riscv/intr) 实现riscv plic驱动,能处理外部中断 (#799)

* feat:(riscv/intr) 实现riscv plic驱动,能处理外部中断

- 实现riscv plic驱动,能处理外部中断
- 能收到virtio-blk的中断
- 实现fasteoi interrupt handler

kernel/src/arch/riscv64/asm/bitops.rs

@@ -4,6 +4,7 @@
 /// @param x 目标u64
 /// @return i32 bit-number(0..63) of the first (least significant) zero bit.
 #[inline]
+#[allow(dead_code)]
 pub fn ffz(x: u64) -> i32 {
     (!x).trailing_zeros() as i32
 }

kernel/src/arch/riscv64/driver/of.rs

@@ -3,7 +3,6 @@ use system_error::SystemError;
 use crate::{
     driver::open_firmware::fdt::OpenFirmwareFdtDriver,
     init::boot_params,
-    kdebug,
     libs::align::page_align_up,
     mm::{mmio_buddy::mmio_pool, MemoryManagementArch, PhysAddr},
 };

kernel/src/arch/riscv64/interrupt/entry.rs

@@ -1,7 +1,5 @@
 use crate::arch::{
-    asm::csr::{
-        CSR_SCAUSE, CSR_SEPC, CSR_SSCRATCH, CSR_SSTATUS, CSR_STVAL, SR_FS_VS, SR_SPP, SR_SUM,
-    },
+    asm::csr::{CSR_SCAUSE, CSR_SEPC, CSR_SSCRATCH, CSR_SSTATUS, CSR_STVAL, SR_SPP},
     cpu::LocalContext,
     interrupt::TrapFrame,
 };

kernel/src/arch/riscv64/interrupt/handle.rs

@@ -5,9 +5,7 @@ use core::hint::spin_loop;
 
 use system_error::SystemError;
 
-use crate::{
-    arch::syscall::syscall_handler, driver::irqchip::riscv_intc::riscv_intc_irq, kdebug, kerror,
-};
+use crate::{arch::syscall::syscall_handler, driver::irqchip::riscv_intc::riscv_intc_irq, kerror};
 
 use super::TrapFrame;
 

kernel/src/arch/riscv64/interrupt/mod.rs

@@ -2,7 +2,7 @@ use riscv::register::{scause::Scause, sstatus::Sstatus};
 use system_error::SystemError;
 
 use crate::{
-    driver::irqchip::riscv_intc::riscv_intc_init,
+    driver::irqchip::{riscv_intc::riscv_intc_init, riscv_sifive_plic::riscv_sifive_plic_init},
     exception::{InterruptArch, IrqFlags, IrqFlagsGuard, IrqNumber},
     libs::align::align_up,
 };
@@ -17,6 +17,9 @@ pub struct RiscV64InterruptArch;
 
 impl InterruptArch for RiscV64InterruptArch {
     unsafe fn arch_irq_init() -> Result<(), SystemError> {
+        Self::interrupt_disable();
+        riscv_sifive_plic_init()?;
+        // 注意，intc的初始化必须在plic之后，不然会导致plic无法关联上中断
         riscv_intc_init()?;
 
         Ok(())

kernel/src/arch/riscv64/mm/mod.rs

@@ -43,6 +43,7 @@ pub struct RiscV64MMArch;
 
 impl RiscV64MMArch {
     /// 使远程cpu的TLB中，指定地址范围的页失效
+    #[allow(dead_code)]
     pub fn remote_invalidate_page(
         cpu: ProcessorId,
         address: VirtAddr,
@@ -57,6 +58,7 @@ impl RiscV64MMArch {
     }
 
     /// 使指定远程cpu的TLB中，所有范围的页失效
+    #[allow(dead_code)]
     pub fn remote_invalidate_all(cpu: ProcessorId) -> Result<(), SbiRet> {
         let r = Self::remote_invalidate_page(
             cpu,

kernel/src/arch/x86_64/driver/apic/lapic_vector.rs

@@ -227,16 +227,23 @@ pub fn x86_vector_domain() -> &'static Arc<IrqDomain> {
 
 #[inline(never)]
 pub fn arch_early_irq_init() -> Result<(), SystemError> {
+    const IRQ_SIZE: u32 = 223;
     let vec_domain = irq_domain_manager()
         .create_and_add(
             "VECTOR".to_string(),
             &X86VectorDomainOps,
             IrqNumber::new(32),
             HardwareIrqNumber::new(32),
-            223,
+            IRQ_SIZE,
         )
         .ok_or(SystemError::ENOMEM)?;
     irq_domain_manager().set_default_domain(vec_domain.clone());
+    irq_domain_manager().domain_associate_many(
+        &vec_domain,
+        IrqNumber::new(0),
+        HardwareIrqNumber::new(0),
+        IRQ_SIZE,
+    );
     unsafe { X86_VECTOR_DOMAIN = Some(vec_domain) };
 
     let apic_chip = Arc::new(LocalApicChip::new());