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riscv: 把内核编译target改为riscv64gc & 获取time csr的频率 & 修正浮点保存与恢复的汇编的问题 (#699)

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* 1. 把内核编译target改为riscv64gc
2. fix: 修正浮点保存与恢复的汇编的问题

* riscv: 获取time csr的频率
This commit is contained in:
LoGin
2024-04-06 22:13:26 +08:00
committed by GitHub
parent f0c87a897f
commit 23ef2b33d1
28 changed files with 373 additions and 229 deletions
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2
.vscode/settings.json vendored
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@ -152,7 +152,7 @@
"./tools/Cargo.toml",
],
// "rust-analyzer.cargo.target": "riscv64imac-unknown-none-elf",
// "rust-analyzer.cargo.target": "riscv64gc-unknown-none-elf",
"rust-analyzer.cargo.target": "x86_64-unknown-none",
"rust-analyzer.check.overrideCommand": [
"make",