riscv: 把内核编译target改为riscv64gc & 获取time csr的频率 & 修正浮点保存与恢复的汇编的问题 (#699)

* 1. 把内核编译target改为riscv64gc
2. fix: 修正浮点保存与恢复的汇编的问题

* riscv: 获取time csr的频率

build-scripts/kernel_build/src/cfiles/arch/riscv64.rs

@@ -31,8 +31,9 @@ impl CFilesArch for RiscV64CFilesArch {
         // // c.flag("-march=rv64imafdc");
         // c.no_default_flags(true);
         c.flag("-mcmodel=medany");
-        c.flag("-mabi=lp64");
-        c.flag("-march=rv64imac");
+
+        c.flag("-mabi=lp64d");
+        c.flag("-march=rv64gc");
     }
 }
 

build-scripts/kernel_build/src/lib.rs

@@ -1,3 +1,5 @@
+#![feature(cfg_target_abi)]
+
 #[macro_use]
 extern crate lazy_static;
 extern crate cc;