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riscv: 把内核编译target改为riscv64gc & 获取time csr的频率 & 修正浮点保存与恢复的汇编的问题 (#699)

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* 1. 把内核编译target改为riscv64gc
2. fix: 修正浮点保存与恢复的汇编的问题

* riscv: 获取time csr的频率
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LoGin
2024-04-06 22:13:26 +08:00
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parent f0c87a897f
commit 23ef2b33d1
28 changed files with 373 additions and 229 deletions
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docs/kernel/configuration/arch.md
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@ -9,7 +9,7 @@
为了能支持vscode的调试功能，我们需要修改`.vscode/settings.json`文件的以下行：
```
"rust-analyzer.cargo.target": "riscv64imac-unknown-none-elf",
"rust-analyzer.cargo.target": "riscv64gc-unknown-none-elf",
// "rust-analyzer.cargo.target": "x86_64-unknown-none",
```