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riscv: 把内核编译target改为riscv64gc & 获取time csr的频率 & 修正浮点保存与恢复的汇编的问题 (#699)

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* 1. 把内核编译target改为riscv64gc
2. fix: 修正浮点保存与恢复的汇编的问题

* riscv: 获取time csr的频率
This commit is contained in:
LoGin
2024-04-06 22:13:26 +08:00
committed by GitHub
parent f0c87a897f
commit 23ef2b33d1
28 changed files with 373 additions and 229 deletions
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2
kernel/env.mk
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@ -36,7 +36,7 @@ export GLOBAL_CFLAGS := -fno-builtin -fno-stack-protector -D $(CFLAGS_DEFINE_ARC
ifeq ($(ARCH), x86_64)
GLOBAL_CFLAGS += -mcmodel=large -m64
else ifeq ($(ARCH), riscv64)
GLOBAL_CFLAGS += -mcmodel=medany -march=rv64imac -mabi=lp64
GLOBAL_CFLAGS += -mcmodel=medany -march=rv64gc -mabi=lp64d
endif
ifeq ($(DEBUG), DEBUG)