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riscv: 把内核编译target改为riscv64gc & 获取time csr的频率 & 修正浮点保存与恢复的汇编的问题 (#699)

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* 1. 把内核编译target改为riscv64gc
2. fix: 修正浮点保存与恢复的汇编的问题

* riscv: 获取time csr的频率
This commit is contained in:
LoGin
2024-04-06 22:13:26 +08:00
committed by GitHub
parent f0c87a897f
commit 23ef2b33d1
28 changed files with 373 additions and 229 deletions
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5
kernel/src/arch/x86_64/mm/mod.rs
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@ -23,7 +23,7 @@ use crate::{
};
use crate::mm::kernel_mapper::KernelMapper;
use crate::mm::page::{PageEntry, PageFlags};
use crate::mm::page::{PageEntry, PageFlags, PAGE_1G_SHIFT};
use crate::mm::{MemoryManagementArch, PageTableKind, PhysAddr, VirtAddr};
use crate::{kdebug, kinfo, kwarn};
use system_error::SystemError;
@ -122,6 +122,9 @@ impl MemoryManagementArch for X86_64MMArch {
/// 设置FIXMAP区域大小为1M
const FIXMAP_SIZE: usize = 256 * 4096;
const MMIO_BASE: VirtAddr = VirtAddr::new(0xffffa10000000000);
const MMIO_SIZE: usize = 1 << PAGE_1G_SHIFT;
/// @brief 获取物理内存区域
unsafe fn init() {
extern "C" {