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Code Issues Releases Wiki Activity

feat(log): 将内核日志统一为新的logger (#814)

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曾俊
2024-05-16 17:25:23 +08:00
committed by GitHub
parent 92deae638b
commit 2eab6dd743
181 changed files with 1321 additions and 1261 deletions
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5
kernel/src/driver/irqchip/riscv_intc.rs
View File

@ -1,4 +1,5 @@
use alloc::{string::ToString, sync::Arc};
use log::error;
use system_error::SystemError;
use crate::{
@ -155,7 +156,7 @@ pub unsafe fn riscv_intc_init() -> Result<(), SystemError> {
RiscvIntcChip::IRQ_SIZE,
)
.ok_or_else(|| {
kerror!("Failed to create riscv-intc domain");
error!("Failed to create riscv-intc domain");
SystemError::ENXIO
})?;
@ -197,7 +198,7 @@ pub fn riscv_intc_assicate_irq(hwirq: HardwareIrqNumber) -> Option<IrqNumber> {
irq_domain_manager()
.domain_associate(
riscv_intc_domain().as_ref().or_else(|| {
kerror!("riscv_intc_domain is None");
error!("riscv_intc_domain is None");
None
})?,
virq,

35
kernel/src/driver/irqchip/riscv_sifive_plic.rs
View File

@ -25,6 +25,7 @@ use alloc::{
};
use bitmap::AllocBitmap;
use fdt::node::FdtNode;
use log::{debug, warn};
use system_error::SystemError;
use crate::{
@ -187,7 +188,7 @@ impl PlicHandler {
fn plic_irq_toggle(cpumask: &CpuMask, irq_data: &Arc<IrqData>, enable: bool) {
cpumask.iter_cpu().for_each(|cpu| {
kdebug!("plic: irq_toggle: cpu: {cpu:?}");
debug!("plic: irq_toggle: cpu: {cpu:?}");
let handler = unsafe { plic_handlers().force_get(cpu) };
handler.toggle(irq_data.hardware_irq(), enable);
});
@ -240,7 +241,7 @@ impl IrqChip for PlicIrqChip {
"SiFive PLIC"
}
fn irq_enable(&self, irq_data: &Arc<IrqData>) -> Result<(), SystemError> {
// kwarn!("plic: irq_enable");
// warn!("plic: irq_enable");
let common_data = irq_data.common_data();
let inner_guard = common_data.inner();
let mask = inner_guard.effective_affinity();
@ -252,7 +253,7 @@ impl IrqChip for PlicIrqChip {
}
fn irq_unmask(&self, irq_data: &Arc<IrqData>) -> Result<(), SystemError> {
// kwarn!("plic: irq_unmask");
// warn!("plic: irq_unmask");
let chip_data = irq_data
.chip_info_read_irqsave()
@ -300,7 +301,7 @@ impl IrqChip for PlicIrqChip {
}
fn irq_disable(&self, irq_data: &Arc<IrqData>) {
kdebug!("plic: irq_disable");
debug!("plic: irq_disable");
let common_data = irq_data.common_data();
let inner_guard = common_data.inner();
let mask = inner_guard.effective_affinity();
@ -321,7 +322,7 @@ impl IrqChip for PlicIrqChip {
handler.toggle(irq_data.hardware_irq(), false);
} else {
// kdebug!("plic: irq_eoi: hwirq: {:?}", irq_data.hardware_irq());
// debug!("plic: irq_eoi: hwirq: {:?}", irq_data.hardware_irq());
unsafe {
write_volatile(
(handler.inner().hart_base + PlicIrqChip::CONTEXT_CLAIM).data() as *mut u32,
@ -423,7 +424,7 @@ pub fn riscv_sifive_plic_init() -> Result<(), SystemError> {
});
for node in all_plics {
if let Err(e) = do_riscv_sifive_plic_init(&node) {
kwarn!("Failed to init SiFive PLIC: node: {node:?} {e:?}");
warn!("Failed to init SiFive PLIC: node: {node:?} {e:?}");
}
}
@ -457,7 +458,7 @@ fn do_riscv_sifive_plic_init(fdt_node: &FdtNode) -> Result<(), SystemError> {
.ok_or(SystemError::EINVAL)?
.as_usize()
.ok_or(SystemError::EINVAL)?;
kdebug!(
debug!(
"plic: node: {}, irq_num: {irq_num}, paddr: {paddr:?}, size: {size}",
fdt_node.name
);
@ -465,7 +466,7 @@ fn do_riscv_sifive_plic_init(fdt_node: &FdtNode) -> Result<(), SystemError> {
.interrupts_extended()
.ok_or(SystemError::EINVAL)?
.count();
kdebug!("plic: nr_contexts: {nr_contexts}");
debug!("plic: nr_contexts: {nr_contexts}");
let irq_domain = irq_domain_manager()
.create_and_add_linear(
@ -474,7 +475,7 @@ fn do_riscv_sifive_plic_init(fdt_node: &FdtNode) -> Result<(), SystemError> {
(irq_num + 1) as u32,
)
.ok_or(SystemError::EINVAL)?;
// kdebug!("plic: irq_domain: {irq_domain:?}");
// debug!("plic: irq_domain: {irq_domain:?}");
let priv_data = PlicChipData::new(
Arc::downgrade(&irq_domain),
@ -506,13 +507,13 @@ fn do_riscv_sifive_plic_init(fdt_node: &FdtNode) -> Result<(), SystemError> {
let cpu = ProcessorId::new(i as u32);
let handler = unsafe { plic_handlers().force_get(cpu) };
if handler.present() {
kwarn!("plic: handler {i} already present.");
warn!("plic: handler {i} already present.");
handler.set_threshold(PlicIrqChip::PLIC_ENABLE_THRESHOLD);
loop_done_setup(handler);
continue;
}
kdebug!("plic: setup lmask {cpu:?}.");
debug!("plic: setup lmask {cpu:?}.");
priv_data.lmask().set(cpu, true);
let mut handler_inner = handler.inner();
handler_inner.hart_base =
@ -560,7 +561,7 @@ fn associate_irq_with_plic_domain(
let irq = irq as u32;
let virq = IrqNumber::new(irq);
let hwirq = HardwareIrqNumber::new(irq);
kdebug!("plic: associate irq: {irq}, virq: {virq:?}, hwirq: {hwirq:?}");
debug!("plic: associate irq: {irq}, virq: {virq:?}, hwirq: {hwirq:?}");
irq_domain_manager()
.domain_associate(irq_domain, virq, hwirq)
.ok();
@ -583,7 +584,7 @@ impl IrqDomainOps for PlicIrqDomainOps {
hwirq: HardwareIrqNumber,
virq: IrqNumber,
) -> Result<(), SystemError> {
// kdebug!("plic: map: virq: {virq:?}, hwirq: {hwirq:?}");
// debug!("plic: map: virq: {virq:?}, hwirq: {hwirq:?}");
let chip_data = irq_domain.host_data().ok_or(SystemError::EINVAL)?;
let plic_chip_data = chip_data
@ -613,7 +614,7 @@ impl IrqDomainOps for PlicIrqDomainOps {
_irq_data: &Arc<IrqData>,
_reserve: bool,
) -> Result<(), SystemError> {
kwarn!("plic: activate");
warn!("plic: activate");
loop {}
}
@ -622,7 +623,7 @@ impl IrqDomainOps for PlicIrqDomainOps {
/// 处理PLIC中断
pub(super) fn do_plic_irq(trap_frame: &mut TrapFrame) {
// kdebug!("plic: do_plic_irq");
// debug!("plic: do_plic_irq");
let handler = plic_handlers().get();
let priv_data = handler.priv_data();
@ -648,11 +649,11 @@ pub(super) fn do_plic_irq(trap_frame: &mut TrapFrame) {
if claim == 0 {
break;
}
kdebug!("plic: claim: {claim:?}");
debug!("plic: claim: {claim:?}");
let hwirq = HardwareIrqNumber::new(claim);
if let Err(e) = GenericIrqHandler::handle_domain_irq(domain.clone(), hwirq, trap_frame) {
kwarn!("plic: can't find mapping for hwirq {hwirq:?}, {e:?}");
warn!("plic: can't find mapping for hwirq {hwirq:?}, {e:?}");
}
}
}