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https://github.com/DragonOS-Community/DragonOS.git
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磁盘请求在处理时，切换进程
This commit is contained in:
fslongjin
@ -1,9 +1,13 @@
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#include "ahci.h"
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#include "../../../common/kprint.h"
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#include "../../../mm/slab.h"
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#include <syscall/syscall.h>
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#include <syscall/syscall_num.h>
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struct pci_device_structure_header_t *ahci_devs[MAX_AHCI_DEVICES];
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struct block_device_request_queue ahci_req_queue;
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uint32_t count_ahci_devices = 0;
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uint64_t ahci_port_base_vaddr; // 端口映射base addr
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@ -27,20 +31,20 @@ void ahci_init()
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{
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kinfo("Initializing AHCI...");
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pci_get_device_structure(0x1, 0x6, ahci_devs, &count_ahci_devices);
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if (count_ahci_devices == 0)
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{
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kwarn("There is no AHCI device found on this computer!");
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return;
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}
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// 映射ABAR
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kdebug("phys_2_virt(ahci_devs[0])= %#018lx",(ahci_devs[0]));
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kdebug("((struct pci_device_structure_general_device_t *)phys_2_virt(ahci_devs[0])))->BAR5= %#018lx",((struct pci_device_structure_general_device_t *)(ahci_devs[0]))->BAR5);
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kdebug("phys_2_virt(ahci_devs[0])= %#018lx", (ahci_devs[0]));
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kdebug("((struct pci_device_structure_general_device_t *)phys_2_virt(ahci_devs[0])))->BAR5= %#018lx", ((struct pci_device_structure_general_device_t *)(ahci_devs[0]))->BAR5);
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uint32_t bar5 = ((struct pci_device_structure_general_device_t *)(ahci_devs[0]))->BAR5;
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mm_map_phys_addr(AHCI_MAPPING_BASE, (ul)(bar5) & PAGE_2M_MASK, PAGE_2M_SIZE, PAGE_KERNEL_PAGE | PAGE_PWT | PAGE_PCD);
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mm_map_phys_addr(AHCI_MAPPING_BASE, (ul)(bar5)&PAGE_2M_MASK, PAGE_2M_SIZE, PAGE_KERNEL_PAGE | PAGE_PWT | PAGE_PCD);
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kdebug("ABAR mapped!");
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for (int i = 0; i < count_ahci_devices; ++i)
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for (int i = 0; i < count_ahci_devices; ++i)
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{
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// kdebug("[%d] class_code=%d, sub_class=%d, progIF=%d, ABAR=%#010lx", i, ahci_devs[i]->Class_code, ahci_devs[i]->SubClass, ahci_devs[i]->ProgIF, ((struct pci_device_structure_general_device_t *)(ahci_devs[i]))->BAR5);
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// 赋值HBA_MEM结构体
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@ -54,10 +58,10 @@ void ahci_init()
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kdebug("ahci_port_base_vaddr=%#018lx", ahci_port_base_vaddr);
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ahci_probe_port(0);
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port_rebase(&ahci_devices[0].hba_mem->ports[0], 0);
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// 初始化请求队列
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ahci_req_queue.in_service = NULL;
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list_init(&(ahci_req_queue.queue_list));
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wait_queue_init(&ahci_req_queue.wait_queue_list, NULL);
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ahci_req_queue.request_count = 0;
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kinfo("AHCI initialized.");
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}
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@ -278,6 +282,8 @@ static bool ahci_read(HBA_PORT *port, uint32_t startl, uint32_t starth, uint32_t
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kdebug("slot=%d", slot);
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port->ci = 1 << slot; // Issue command
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sched_cfs();
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int retval = AHCI_SUCCESS;
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// Wait for completion
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while (1)
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{
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@ -288,7 +294,8 @@ static bool ahci_read(HBA_PORT *port, uint32_t startl, uint32_t starth, uint32_t
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if (port->is & HBA_PxIS_TFES) // Task file error
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{
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kerror("Read disk error");
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return E_TASK_FILE_ERROR;
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retval = E_TASK_FILE_ERROR;
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break;
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}
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}
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@ -296,10 +303,10 @@ static bool ahci_read(HBA_PORT *port, uint32_t startl, uint32_t starth, uint32_t
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if (port->is & HBA_PxIS_TFES)
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{
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kerror("Read disk error");
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return E_TASK_FILE_ERROR;
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retval = E_TASK_FILE_ERROR;
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}
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return AHCI_SUCCESS;
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enter_syscall_int(SYS_AHCI_END_REQ, 0, 0, 0, 0, 0, 0, 0, 0);
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return retval;
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}
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static bool ahci_write(HBA_PORT *port, uint32_t startl, uint32_t starth, uint32_t count,
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@ -352,6 +359,10 @@ static bool ahci_write(HBA_PORT *port, uint32_t startl, uint32_t starth, uint32_
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cmdfis->counth = count >> 8;
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// printk("[slot]{%d}", slot);
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port->ci = 1; // Issue command
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sched_cfs();
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int retval = AHCI_SUCCESS;
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while (1)
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{
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// In some longer duration reads, it may be helpful to spin on the DPS bit
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@ -361,16 +372,18 @@ static bool ahci_write(HBA_PORT *port, uint32_t startl, uint32_t starth, uint32_
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if (port->is & HBA_PxIS_TFES)
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{ // Task file error
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kerror("Write disk error");
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return E_TASK_FILE_ERROR;
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retval = E_TASK_FILE_ERROR;
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break;
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}
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}
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if (port->is & HBA_PxIS_TFES)
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{
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kerror("Write disk error");
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return E_TASK_FILE_ERROR;
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retval = E_TASK_FILE_ERROR;
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}
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return AHCI_SUCCESS;
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enter_syscall_int(SYS_AHCI_END_REQ, 0, 0, 0, 0, 0, 0, 0, 0);
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return retval;
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}
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// Find a free command list slot
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@ -410,32 +423,33 @@ long ahci_close()
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* @param port_num ahci控制器端口号
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* @return struct block_device_request_packet*
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*/
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static struct block_device_request_packet *ahci_make_request(long cmd, uint64_t base_addr, uint64_t count, uint64_t buffer, uint8_t ahci_ctrl_num, uint8_t port_num)
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static struct ahci_request_packet_t *ahci_make_request(long cmd, uint64_t base_addr, uint64_t count, uint64_t buffer, uint8_t ahci_ctrl_num, uint8_t port_num)
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{
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struct block_device_request_packet *pack = (struct block_device_request_packet *)kmalloc(sizeof(struct block_device_request_packet), 0);
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struct ahci_request_packet_t *pack = (struct ahci_request_packet_t *)kmalloc(sizeof(struct ahci_request_packet_t), 0);
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list_init(&pack->list);
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wait_queue_init(&pack->blk_pak.wait_queue, current_pcb);
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pack->blk_pak.device_type = BLK_TYPE_AHCI;
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// 由于ahci不需要中断即可读取磁盘，因此end handler为空
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switch (cmd)
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{
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case ATA_CMD_READ_DMA_EXT:
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pack->end_handler = NULL;
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pack->cmd = ATA_CMD_READ_DMA_EXT;
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pack->blk_pak.end_handler = NULL;
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pack->blk_pak.cmd = ATA_CMD_READ_DMA_EXT;
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break;
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case ATA_CMD_WRITE_DMA_EXT:
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pack->end_handler = NULL;
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pack->cmd = ATA_CMD_WRITE_DMA_EXT;
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pack->blk_pak.end_handler = NULL;
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pack->blk_pak.cmd = ATA_CMD_WRITE_DMA_EXT;
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break;
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default:
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pack->end_handler = NULL;
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pack->cmd = cmd;
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pack->blk_pak.end_handler = NULL;
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pack->blk_pak.cmd = cmd;
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break;
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}
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pack->LBA_start = base_addr;
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pack->count = count;
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pack->buffer_vaddr = buffer;
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pack->blk_pak.LBA_start = base_addr;
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pack->blk_pak.count = count;
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pack->blk_pak.buffer_vaddr = buffer;
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pack->ahci_ctrl_num = ahci_ctrl_num;
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pack->port_num = port_num;
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@ -446,8 +460,10 @@ static struct block_device_request_packet *ahci_make_request(long cmd, uint64_t
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* @brief 结束磁盘请求
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*
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*/
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static void ahci_end_request()
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void ahci_end_request()
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{
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ahci_req_queue.in_service->wait_queue.pcb->state = PROC_RUNNING;
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ahci_req_queue.in_service->wait_queue.pcb->flags |= PROC_NEED_SCHED;
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kfree((uint64_t *)ahci_req_queue.in_service);
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ahci_req_queue.in_service = NULL;
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@ -458,27 +474,31 @@ static void ahci_end_request()
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static long ahci_query_disk()
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{
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struct block_device_request_packet *pack = container_of(list_next(&ahci_req_queue.queue_list), struct block_device_request_packet, list);
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ahci_req_queue.in_service = pack;
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list_del(&(ahci_req_queue.in_service->list));
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wait_queue_node_t *wait_queue_tmp = container_of(list_next(&ahci_req_queue.wait_queue_list.wait_list), wait_queue_node_t, wait_list);
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struct ahci_request_packet_t *pack = (struct ahci_request_packet_t *)container_of(wait_queue_tmp, struct block_device_request_packet, wait_queue);
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ahci_req_queue.in_service = (struct block_device_request_packet *)pack;
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list_del(&(ahci_req_queue.in_service->wait_queue.wait_list));
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--ahci_req_queue.request_count;
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long ret_val;
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switch (pack->cmd)
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switch (pack->blk_pak.cmd)
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{
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case ATA_CMD_READ_DMA_EXT:
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ret_val = ahci_read(&(ahci_devices[pack->ahci_ctrl_num].hba_mem->ports[pack->port_num]), pack->LBA_start & 0xFFFFFFFF, ((pack->LBA_start) >> 32) & 0xFFFFFFFF, pack->count, pack->buffer_vaddr);
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ret_val = ahci_read(&(ahci_devices[pack->ahci_ctrl_num].hba_mem->ports[pack->port_num]), pack->blk_pak.LBA_start & 0xFFFFFFFF, ((pack->blk_pak.LBA_start) >> 32) & 0xFFFFFFFF, pack->blk_pak.count, pack->blk_pak.buffer_vaddr);
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break;
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case ATA_CMD_WRITE_DMA_EXT:
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ret_val = ahci_write(&(ahci_devices[pack->ahci_ctrl_num].hba_mem->ports[pack->port_num]), pack->LBA_start & 0xFFFFFFFF, ((pack->LBA_start) >> 32) & 0xFFFFFFFF, pack->count, pack->buffer_vaddr);
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ret_val = ahci_write(&(ahci_devices[pack->ahci_ctrl_num].hba_mem->ports[pack->port_num]), pack->blk_pak.LBA_start & 0xFFFFFFFF, ((pack->blk_pak.LBA_start) >> 32) & 0xFFFFFFFF, pack->blk_pak.count, pack->blk_pak.buffer_vaddr);
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break;
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default:
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kerror("Unsupport ahci command: %#05lx", pack->cmd);
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kerror("Unsupport ahci command: %#05lx", pack->blk_pak.cmd);
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ret_val = E_UNSUPPORTED_CMD;
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break;
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}
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ahci_end_request();
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// ahci_end_request();
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return ret_val;
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}
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@ -487,9 +507,9 @@ static long ahci_query_disk()
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*
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* @param pack
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*/
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static void ahci_submit(struct block_device_request_packet *pack)
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static void ahci_submit(struct ahci_request_packet_t *pack)
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{
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list_append(&(ahci_req_queue.queue_list), &(pack->list));
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list_append(&(ahci_req_queue.wait_queue_list.wait_list), &(pack->blk_pak.wait_queue.wait_list));
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++ahci_req_queue.request_count;
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if (ahci_req_queue.in_service == NULL) // 当前没有正在请求的io包，立即执行磁盘请求
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@ -509,7 +529,7 @@ static void ahci_submit(struct block_device_request_packet *pack)
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*/
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static long ahci_transfer(long cmd, uint64_t base_addr, uint64_t count, uint64_t buf, uint8_t ahci_ctrl_num, uint8_t port_num)
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{
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struct block_device_request_packet *pack = NULL;
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struct ahci_request_packet_t *pack = NULL;
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if (cmd == ATA_CMD_READ_DMA_EXT || cmd == ATA_CMD_WRITE_DMA_EXT)
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{
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@ -6,16 +6,16 @@
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/**
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* @todo 加入io调度器（当操作系统实现了多进程之后要加入这个）
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*
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*
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*/
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#define AHCI_MAPPING_BASE SPECIAL_MEMOEY_MAPPING_VIRT_ADDR_BASE+AHCI_MAPPING_OFFSET
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#define AHCI_MAPPING_BASE SPECIAL_MEMOEY_MAPPING_VIRT_ADDR_BASE + AHCI_MAPPING_OFFSET
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#define MAX_AHCI_DEVICES 100
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#define HBA_PxCMD_ST 0x0001
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#define HBA_PxCMD_FRE 0x0010
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#define HBA_PxCMD_FR 0x4000
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#define HBA_PxCMD_CR 0x8000
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#define HBA_PxCMD_ST 0x0001
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#define HBA_PxCMD_FRE 0x0010
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#define HBA_PxCMD_FR 0x4000
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#define HBA_PxCMD_CR 0x8000
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#define ATA_DEV_BUSY 0x80
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#define ATA_DEV_DRQ 0x08
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@ -23,11 +23,11 @@
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#define ATA_CMD_READ_DMA_EXT 0x25
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#define ATA_CMD_WRITE_DMA_EXT 0x30
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#define HBA_PxIS_TFES (1 << 30) /* TFES - Task File Error Status */
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#define HBA_PxIS_TFES (1 << 30) /* TFES - Task File Error Status */
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#define AHCI_SUCCESS 0 // 请求成功
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#define E_NOEMPTYSLOT 1 // 没有空闲的slot
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#define E_PORT_HUNG 2 // 端口被挂起
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#define AHCI_SUCCESS 0 // 请求成功
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#define E_NOEMPTYSLOT 1 // 没有空闲的slot
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#define E_PORT_HUNG 2 // 端口被挂起
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#define E_TASK_FILE_ERROR 3 // 任务文件错误
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#define E_UNSUPPORTED_CMD 4 // 不支持的命令
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@ -210,169 +210,164 @@ typedef struct tagFIS_DMA_SETUP
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typedef volatile struct tagHBA_PORT
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{
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uint64_t clb; // 0x00, command list base address, 1K-byte aligned
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uint64_t fb; // 0x08, FIS base address, 256-byte aligned
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uint32_t is; // 0x10, interrupt status
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uint32_t ie; // 0x14, interrupt enable
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uint32_t cmd; // 0x18, command and status
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uint32_t rsv0; // 0x1C, Reserved
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uint32_t tfd; // 0x20, task file data
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uint32_t sig; // 0x24, signature
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uint32_t ssts; // 0x28, SATA status (SCR0:SStatus)
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uint32_t sctl; // 0x2C, SATA control (SCR2:SControl)
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uint32_t serr; // 0x30, SATA error (SCR1:SError)
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uint32_t sact; // 0x34, SATA active (SCR3:SActive)
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uint32_t ci; // 0x38, command issue
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uint32_t sntf; // 0x3C, SATA notification (SCR4:SNotification)
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uint32_t fbs; // 0x40, FIS-based switch control
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uint32_t rsv1[11]; // 0x44 ~ 0x6F, Reserved
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uint32_t vendor[4]; // 0x70 ~ 0x7F, vendor specific
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uint64_t clb; // 0x00, command list base address, 1K-byte aligned
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uint64_t fb; // 0x08, FIS base address, 256-byte aligned
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uint32_t is; // 0x10, interrupt status
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uint32_t ie; // 0x14, interrupt enable
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uint32_t cmd; // 0x18, command and status
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uint32_t rsv0; // 0x1C, Reserved
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uint32_t tfd; // 0x20, task file data
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uint32_t sig; // 0x24, signature
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uint32_t ssts; // 0x28, SATA status (SCR0:SStatus)
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uint32_t sctl; // 0x2C, SATA control (SCR2:SControl)
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uint32_t serr; // 0x30, SATA error (SCR1:SError)
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uint32_t sact; // 0x34, SATA active (SCR3:SActive)
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uint32_t ci; // 0x38, command issue
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uint32_t sntf; // 0x3C, SATA notification (SCR4:SNotification)
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uint32_t fbs; // 0x40, FIS-based switch control
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uint32_t rsv1[11]; // 0x44 ~ 0x6F, Reserved
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uint32_t vendor[4]; // 0x70 ~ 0x7F, vendor specific
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} HBA_PORT;
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typedef volatile struct tagHBA_MEM
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{
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// 0x00 - 0x2B, Generic Host Control
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uint32_t cap; // 0x00, Host capability
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uint32_t ghc; // 0x04, Global host control
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uint32_t is; // 0x08, Interrupt status
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uint32_t pi; // 0x0C, Port implemented
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uint32_t vs; // 0x10, Version
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uint32_t ccc_ctl; // 0x14, Command completion coalescing control
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uint32_t ccc_pts; // 0x18, Command completion coalescing ports
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uint32_t em_loc; // 0x1C, Enclosure management location
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uint32_t em_ctl; // 0x20, Enclosure management control
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uint32_t cap2; // 0x24, Host capabilities extended
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uint32_t bohc; // 0x28, BIOS/OS handoff control and status
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// 0x2C - 0x9F, Reserved
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uint8_t rsv[0xA0-0x2C];
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// 0xA0 - 0xFF, Vendor specific registers
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uint8_t vendor[0x100-0xA0];
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// 0x100 - 0x10FF, Port control registers
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HBA_PORT ports[32]; // 1 ~ 32
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// 0x00 - 0x2B, Generic Host Control
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uint32_t cap; // 0x00, Host capability
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uint32_t ghc; // 0x04, Global host control
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uint32_t is; // 0x08, Interrupt status
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uint32_t pi; // 0x0C, Port implemented
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uint32_t vs; // 0x10, Version
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uint32_t ccc_ctl; // 0x14, Command completion coalescing control
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uint32_t ccc_pts; // 0x18, Command completion coalescing ports
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uint32_t em_loc; // 0x1C, Enclosure management location
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uint32_t em_ctl; // 0x20, Enclosure management control
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uint32_t cap2; // 0x24, Host capabilities extended
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uint32_t bohc; // 0x28, BIOS/OS handoff control and status
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// 0x2C - 0x9F, Reserved
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uint8_t rsv[0xA0 - 0x2C];
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||||
// 0xA0 - 0xFF, Vendor specific registers
|
||||
uint8_t vendor[0x100 - 0xA0];
|
||||
|
||||
// 0x100 - 0x10FF, Port control registers
|
||||
HBA_PORT ports[32]; // 1 ~ 32
|
||||
} HBA_MEM;
|
||||
|
||||
|
||||
// There are four kinds of FIS which may be sent to the host by the device as indicated in the following structure declaration.
|
||||
//
|
||||
//
|
||||
typedef volatile struct tagHBA_FIS
|
||||
{
|
||||
// 0x00
|
||||
FIS_DMA_SETUP dsfis; // DMA Setup FIS
|
||||
uint8_t pad0[4];
|
||||
|
||||
// 0x20
|
||||
FIS_PIO_SETUP psfis; // PIO Setup FIS
|
||||
uint8_t pad1[12];
|
||||
|
||||
// 0x40
|
||||
FIS_REG_D2H rfis; // Register – Device to Host FIS
|
||||
uint8_t pad2[4];
|
||||
|
||||
// 0x58
|
||||
//FIS_DEV_BITS sdbfis; // Set Device Bit FIS
|
||||
|
||||
// 0x60
|
||||
uint8_t ufis[64];
|
||||
|
||||
// 0xA0
|
||||
uint8_t rsv[0x100-0xA0];
|
||||
// 0x00
|
||||
FIS_DMA_SETUP dsfis; // DMA Setup FIS
|
||||
uint8_t pad0[4];
|
||||
|
||||
// 0x20
|
||||
FIS_PIO_SETUP psfis; // PIO Setup FIS
|
||||
uint8_t pad1[12];
|
||||
|
||||
// 0x40
|
||||
FIS_REG_D2H rfis; // Register – Device to Host FIS
|
||||
uint8_t pad2[4];
|
||||
|
||||
// 0x58
|
||||
// FIS_DEV_BITS sdbfis; // Set Device Bit FIS
|
||||
|
||||
// 0x60
|
||||
uint8_t ufis[64];
|
||||
|
||||
// 0xA0
|
||||
uint8_t rsv[0x100 - 0xA0];
|
||||
} HBA_FIS;
|
||||
|
||||
typedef struct tagHBA_CMD_HEADER
|
||||
{
|
||||
// DW0
|
||||
uint8_t cfl:5; // Command FIS length in DWORDS, 2 ~ 16
|
||||
uint8_t a:1; // ATAPI
|
||||
uint8_t w:1; // Write, 1: H2D, 0: D2H
|
||||
uint8_t p:1; // Prefetchable
|
||||
|
||||
uint8_t r:1; // Reset
|
||||
uint8_t b:1; // BIST
|
||||
uint8_t c:1; // Clear busy upon R_OK
|
||||
uint8_t rsv0:1; // Reserved
|
||||
uint8_t pmp:4; // Port multiplier port
|
||||
|
||||
uint16_t prdtl; // Physical region descriptor table length in entries
|
||||
|
||||
// DW1
|
||||
volatile
|
||||
uint32_t prdbc; // Physical region descriptor byte count transferred
|
||||
|
||||
// DW2, 3
|
||||
uint64_t ctba; // Command table descriptor base address
|
||||
|
||||
// DW4 - 7
|
||||
uint32_t rsv1[4]; // Reserved
|
||||
// DW0
|
||||
uint8_t cfl : 5; // Command FIS length in DWORDS, 2 ~ 16
|
||||
uint8_t a : 1; // ATAPI
|
||||
uint8_t w : 1; // Write, 1: H2D, 0: D2H
|
||||
uint8_t p : 1; // Prefetchable
|
||||
|
||||
uint8_t r : 1; // Reset
|
||||
uint8_t b : 1; // BIST
|
||||
uint8_t c : 1; // Clear busy upon R_OK
|
||||
uint8_t rsv0 : 1; // Reserved
|
||||
uint8_t pmp : 4; // Port multiplier port
|
||||
|
||||
uint16_t prdtl; // Physical region descriptor table length in entries
|
||||
|
||||
// DW1
|
||||
volatile uint32_t prdbc; // Physical region descriptor byte count transferred
|
||||
|
||||
// DW2, 3
|
||||
uint64_t ctba; // Command table descriptor base address
|
||||
|
||||
// DW4 - 7
|
||||
uint32_t rsv1[4]; // Reserved
|
||||
} HBA_CMD_HEADER;
|
||||
|
||||
typedef struct tagHBA_PRDT_ENTRY
|
||||
{
|
||||
uint64_t dba; // Data base address
|
||||
uint32_t rsv0; // Reserved
|
||||
|
||||
// DW3
|
||||
uint32_t dbc:22; // Byte count, 4M max
|
||||
uint32_t rsv1:9; // Reserved
|
||||
uint32_t i:1; // Interrupt on completion
|
||||
} HBA_PRDT_ENTRY;
|
||||
uint64_t dba; // Data base address
|
||||
uint32_t rsv0; // Reserved
|
||||
|
||||
// DW3
|
||||
uint32_t dbc : 22; // Byte count, 4M max
|
||||
uint32_t rsv1 : 9; // Reserved
|
||||
uint32_t i : 1; // Interrupt on completion
|
||||
} HBA_PRDT_ENTRY;
|
||||
|
||||
typedef struct tagHBA_CMD_TBL
|
||||
{
|
||||
// 0x00
|
||||
uint8_t cfis[64]; // Command FIS
|
||||
|
||||
// 0x40
|
||||
uint8_t acmd[16]; // ATAPI command, 12 or 16 bytes
|
||||
|
||||
// 0x50
|
||||
uint8_t rsv[48]; // Reserved
|
||||
|
||||
// 0x80
|
||||
HBA_PRDT_ENTRY prdt_entry[1]; // Physical region descriptor table entries, 0 ~ 65535
|
||||
// 0x00
|
||||
uint8_t cfis[64]; // Command FIS
|
||||
|
||||
// 0x40
|
||||
uint8_t acmd[16]; // ATAPI command, 12 or 16 bytes
|
||||
|
||||
// 0x50
|
||||
uint8_t rsv[48]; // Reserved
|
||||
|
||||
// 0x80
|
||||
HBA_PRDT_ENTRY prdt_entry[1]; // Physical region descriptor table entries, 0 ~ 65535
|
||||
} HBA_CMD_TBL;
|
||||
|
||||
struct ahci_device_t
|
||||
{
|
||||
uint32_t type; // 设备类型
|
||||
struct pci_device_structure_header_t * dev_struct;
|
||||
HBA_MEM * hba_mem;
|
||||
}ahci_devices[MAX_AHCI_DEVICES];
|
||||
uint32_t type; // 设备类型
|
||||
struct pci_device_structure_header_t *dev_struct;
|
||||
HBA_MEM *hba_mem;
|
||||
} ahci_devices[MAX_AHCI_DEVICES];
|
||||
|
||||
#define SATA_SIG_ATA 0x00000101 // SATA drive
|
||||
#define SATA_SIG_ATAPI 0xEB140101 // SATAPI drive
|
||||
#define SATA_SIG_SEMB 0xC33C0101 // Enclosure management bridge
|
||||
#define SATA_SIG_PM 0x96690101 // Port multiplier
|
||||
|
||||
#define SATA_SIG_ATA 0x00000101 // SATA drive
|
||||
#define SATA_SIG_ATAPI 0xEB140101 // SATAPI drive
|
||||
#define SATA_SIG_SEMB 0xC33C0101 // Enclosure management bridge
|
||||
#define SATA_SIG_PM 0x96690101 // Port multiplier
|
||||
|
||||
#define AHCI_DEV_NULL 0
|
||||
#define AHCI_DEV_SATA 1
|
||||
#define AHCI_DEV_SEMB 2
|
||||
#define AHCI_DEV_PM 3
|
||||
#define AHCI_DEV_SATAPI 4
|
||||
|
||||
|
||||
#define HBA_PORT_IPM_ACTIVE 1
|
||||
#define HBA_PORT_DET_PRESENT 3
|
||||
|
||||
|
||||
|
||||
struct block_device_request_queue ahci_req_queue;
|
||||
|
||||
|
||||
|
||||
|
||||
struct ahci_request_packet_t
|
||||
{
|
||||
struct block_device_request_packet blk_pak; // 块设备请求包
|
||||
uint8_t ahci_ctrl_num; // ahci控制器号， 默认应为0
|
||||
uint8_t port_num; // ahci的设备端口号
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief 初始化ahci模块
|
||||
*
|
||||
*
|
||||
*/
|
||||
void ahci_init();
|
||||
|
||||
/**
|
||||
* @brief 检测端口连接的设备的类型
|
||||
*
|
||||
*
|
||||
* @param device_num ahci设备号
|
||||
*/
|
||||
static void ahci_probe_port(const uint32_t device_num);
|
||||
@ -402,4 +397,6 @@ static bool ahci_read(HBA_PORT *port, uint32_t startl, uint32_t starth, uint32_t
|
||||
* @return false failed
|
||||
*/
|
||||
static bool ahci_write(HBA_PORT *port, uint32_t startl, uint32_t starth, uint32_t count,
|
||||
uint64_t buf);
|
||||
uint64_t buf);
|
||||
|
||||
void ahci_end_request();
|
||||
@ -2,7 +2,9 @@
|
||||
|
||||
#include "../../common/glib.h"
|
||||
#include "stdint.h"
|
||||
#include <process/semaphore.h>
|
||||
|
||||
#define BLK_TYPE_AHCI 0
|
||||
struct block_device_operation
|
||||
{
|
||||
long (*open)();
|
||||
@ -22,11 +24,10 @@ struct block_device_request_packet
|
||||
uint32_t count;
|
||||
uint64_t buffer_vaddr;
|
||||
|
||||
uint8_t ahci_ctrl_num; // ahci控制器号， 默认应为0
|
||||
uint8_t port_num; // ahci的设备端口号
|
||||
uint8_t device_type; // 0: ahci
|
||||
void (*end_handler)(ul num, ul arg);
|
||||
|
||||
struct List list;
|
||||
wait_queue_node_t wait_queue;
|
||||
};
|
||||
|
||||
/**
|
||||
@ -35,7 +36,7 @@ struct block_device_request_packet
|
||||
*/
|
||||
struct block_device_request_queue
|
||||
{
|
||||
struct List queue_list;
|
||||
wait_queue_node_t wait_queue_list;
|
||||
struct block_device_request_packet * in_service; // 正在请求的结点
|
||||
ul request_count;
|
||||
};
|
||||
Reference in New Issue
Block a user