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🆕 pci驱动的数据结构
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fslongjin
parent
046bce39a9
commit
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@ -39,6 +39,7 @@
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})
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// 定义类型的缩写
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typedef unsigned char uchar;
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typedef unsigned short ushort;
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typedef unsigned int uint;
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typedef unsigned long ul;
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29
kernel/driver/pci/pci.c
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29
kernel/driver/pci/pci.c
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#include "pci.h"
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#include "../../common/kprint.h"
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/**
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* @brief 从pci配置空间读取信息
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*
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* @param bus 总线号
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* @param slot 设备号
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* @param func 功能号
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* @param offset 寄存器偏移量
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* @return uint 寄存器值
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*/
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uint pci_read_config(uchar bus, uchar slot, uchar func, uchar offset)
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{
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uint lbus = (uint)bus;
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uint lslot = (uint)slot;
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uint lfunc = ((uint)func) & 7;
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// 构造pci配置空间地址
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uint address = (uint)((lbus << 16) | (lslot << 11) | (lfunc << 8)|(offset&0xfc)|((uint)0x80000000));
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io_out32(PORT_PCI_CONFIG_ADDRESS, address);
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// 读取返回的数据
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return (uint)(io_in32(PORT_PCI_CONFIG_DATA));
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}
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void pci_init()
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{
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}
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165
kernel/driver/pci/pci.h
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165
kernel/driver/pci/pci.h
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#pragma once
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#include "../../common/glib.h"
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#include "stdint.h"
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#define PORT_PCI_CONFIG_ADDRESS 0xcf8
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#define PORT_PCI_CONFIG_DATA 0xcfc
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/**
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* @brief 初始化pci驱动
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*
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*/
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void pci_init();
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// pci设备结构的通用标题字段
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struct pci_device_structure_header_t
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{
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uint16_t Vendor_ID; // 供应商ID 0xffff是一个无效值，在读取访问不存在的设备的配置空间寄存器时返回
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uint16_t Device_ID; // 设备ID，标志特定设备
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uint16_t Command; // 提供对设备生成和响应pci周期的能力的控制 向该寄存器写入0时，设备与pci总线断开除配置空间访问以外的所有连接
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uint16_t Status; // 用于记录pci总线相关时间的状态信息寄存器
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uint8_t RevisionID; // 修订ID，指定特定设备的修订标志符
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uint8_t ProgIF; // 编程接口字节，一个只读寄存器，指定设备具有的寄存器级别的编程接口（如果有的话）
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uint8_t SubClass; // 子类。指定设备执行的特定功能的只读寄存器
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uint8_t Class_code; // 类代码，一个只读寄存器，指定设备执行的功能类型
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uint8_t CacheLineSize; // 缓存线大小：以 32 位为单位指定系统缓存线大小。设备可以限制它可以支持的缓存线大小的数量，如果不支持的值写入该字段，设备将表现得好像写入了 0 值
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uint8_t LatencyTimer; // 延迟计时器：以 PCI 总线时钟为单位指定延迟计时器。
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uint8_t HeaderType; // 标头类型 a value of 0x0 specifies a general device, a value of 0x1 specifies a PCI-to-PCI bridge, and a value of 0x2 specifies a CardBus bridge. If bit 7 of this register is set, the device has multiple functions; otherwise, it is a single function device.
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uint8_t BIST; // Represents that status and allows control of a devices BIST (built-in self test).
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// Here is the layout of the BIST register:
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// | bit7 | bit6 | Bits 5-4 | Bits 3-0 |
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// | BIST Capable | Start BIST | Reserved | Completion Code |
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// for more details, please visit https://wiki.osdev.org/PCI
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} __attribute__((packed));
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/**
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* @brief 表头类型为0x0的pci设备结构
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*
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*/
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struct pci_device_structure_general_device_t
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{
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struct pci_device_structure_header_t header;
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uint32_t BAR0;
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uint32_t BAR1;
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uint32_t BAR2;
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uint32_t BAR3;
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uint32_t BAR4;
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uint32_t BAR5;
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uint32_t Cardbus_CIS_Pointer; // 指向卡信息结构，供在 CardBus 和 PCI 之间共享芯片的设备使用。
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uint16_t Subsystem_Vendor_ID;
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uint16_t Subsystem_ID;
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uint32_t Expansion_ROM_base_address;
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uint8_t Capabilities_Pointer;
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uint8_t reserved0;
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uint16_t reserved1;
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uint32_t reserved2;
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uint8_t Interrupt_Line; // 指定设备的中断引脚连接到系统中断控制器的哪个输入，并由任何使用中断引脚的设备实现。对于 x86 架构，此寄存器对应于 PIC IRQ 编号 0-15（而不是 I/O APIC IRQ 编号），并且值0xFF定义为无连接。
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uint8_t Interrupt_PIN; // 指定设备使用的中断引脚。其中值为0x1INTA#、0x2INTB#、0x3INTC#、0x4INTD#，0x0表示设备不使用中断引脚。
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uint8_t Min_Grant; // 一个只读寄存器，用于指定设备所需的突发周期长度（以 1/4 微秒为单位）（假设时钟速率为 33 MHz）
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uint8_t Max_Latency; // 一个只读寄存器，指定设备需要多长时间访问一次 PCI 总线（以 1/4 微秒为单位）。
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} __attribute__((packed));
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/**
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* @brief 表头类型为0x1的pci设备结构（PCI to PCI Bridge）
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*
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*/
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struct pci_device_structure_pci_to_pci_bridge_t
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{
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struct pci_device_structure_header_t header;
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uint32_t BAR0;
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uint32_t BAR1;
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uint8_t Primary_Bus_Number;
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uint8_t Secondary_Bus_Number;
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uint8_t Subordinate_Bus_Number;
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uint8_t Secondary_Latency_Timer;
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uint8_t io_base;
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uint8_t io_limit;
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uint16_t Secondary_Status;
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uint16_t Memory_Base;
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uint16_t Memory_Limit;
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uint16_t Prefetchable_Memory_Base;
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uint16_t Prefetchable_Memory_Limit;
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uint32_t Prefetchable_Base_Upper_32_Bits;
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uint32_t Prefetchable_Limit_Upper_32_Bits;
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uint16_t io_Base_Upper_16_Bits;
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uint16_t io_Limit_Upper_16_Bits;
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uint8_t Capability_Pointer;
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uint8_t reserved0;
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uint16_t reserved1;
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uint32_t Expansion_ROM_base_address;
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uint8_t Interrupt_Line;
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uint8_t Interrupt_PIN;
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uint16_t Bridge_Control;
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} __attribute__((packed));
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/**
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* @brief 表头类型为0x2的pci设备结构（PCI to CardBus Bridge）
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*
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*/
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struct pci_device_structure_pci_to_cardbus_bridge_t
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{
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struct pci_device_structure_header_t header;
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uint32_t CardBus_Socket_ExCa_base_address;
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uint8_t Offset_of_capabilities_list;
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uint8_t Reserved;
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uint16_t Secondary_status;
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uint8_t PCI_bus_number;
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uint8_t CardBus_bus_number;
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uint8_t Subordinate_bus_number;
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uint8_t CardBus_latency_timer;
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uint32_t Memory_Base_Address0;
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uint32_t Memory_Limit0;
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uint32_t Memory_Base_Address1;
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uint32_t Memory_Limit1;
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uint32_t IO_Base_Address0;
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uint32_t IO_Limit0;
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uint32_t IO_Base_Address1;
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uint32_t IO_Limit1;
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uint8_t Interrupt_Line;
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uint8_t Interrupt_PIN;
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uint16_t Bridge_Control;
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uint16_t Subsystem_Device_ID;
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uint16_t Subsystem_Vendor_ID;
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uint32_t PC_Card_legacy_mode_base_address_16_bit;
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} __attribute__((packed));
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/**
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* @brief 从pci配置空间读取信息
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*
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* @param bus 总线号
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* @param slot 插槽号
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* @param func 功能号
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* @param offset 寄存器偏移量
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* @return uint 寄存器值
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*/
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uint pci_read_config(uchar bus, uchar slot, uchar func, uchar offset);
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