mirror of
https://github.com/DragonOS-Community/DragonOS.git
synced 2025-06-19 00:46:31 +00:00
🆕 按照class来读取对应的pci设备的接口
This commit is contained in:
@ -19,10 +19,10 @@ all: kernel
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objcopy -I elf64-x86-64 -S -R ".comment" -R ".eh_frame" -O elf64-x86-64 kernel ../bin/kernel/kernel.elf
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objcopy -I elf64-x86-64 -S -R ".comment" -R ".eh_frame" -O elf64-x86-64 kernel ../bin/kernel/kernel.elf
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kernel: head.o entry.o main.o printk.o trap.o mm.o slab.o irq.o pic.o process.o syscall.o multiboot2.o cpu.o acpi.o ps2_keyboard.o ps2_mouse.o ata.o pci.o
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kernel: head.o entry.o main.o printk.o trap.o mm.o slab.o irq.o pic.o process.o syscall.o multiboot2.o cpu.o acpi.o ps2_keyboard.o ps2_mouse.o ata.o pci.o ahci.o
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ld -b elf64-x86-64 -z muldefs -o kernel head.o exception/entry.o main.o common/printk.o exception/trap.o exception/irq.o mm/mm.o mm/slab.o process/process.o syscall/syscall.o driver/multiboot2/multiboot2.o \
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ld -b elf64-x86-64 -z muldefs -o kernel head.o exception/entry.o main.o common/printk.o exception/trap.o exception/irq.o mm/mm.o mm/slab.o process/process.o syscall/syscall.o driver/multiboot2/multiboot2.o \
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common/cpu.o \
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common/cpu.o \
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driver/acpi/acpi.o driver/interrupt/pic.o driver/keyboard/ps2_keyboard.o driver/mouse/ps2_mouse.o driver/disk/ata.o driver/pci/pci.o \
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driver/acpi/acpi.o driver/interrupt/pic.o driver/keyboard/ps2_keyboard.o driver/mouse/ps2_mouse.o driver/disk/ata.o driver/pci/pci.o driver/disk/ahci/ahci.o \
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-T link.lds
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-T link.lds
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head.o: head.S
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head.o: head.S
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@ -97,6 +97,9 @@ ata.o: driver/disk/ata.c
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pci.o: driver/pci/pci.c
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pci.o: driver/pci/pci.c
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gcc $(CFLAGS) -c driver/pci/pci.c -o driver/pci/pci.o
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gcc $(CFLAGS) -c driver/pci/pci.c -o driver/pci/pci.o
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ahci.o: driver/disk/ahci/ahci.c
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gcc $(CFLAGS) -c driver/disk/ahci/ahci.c -o driver/disk/ahci/ahci.o
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clean:
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clean:
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rm -rf $(GARBAGE)
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rm -rf $(GARBAGE)
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@ -1,3 +1,19 @@
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#include "ahci.h"
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#include "ahci.h"
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#include "../../../common/kprint.h"
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#include "../../../common/kprint.h"
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struct pci_device_structure_header_t *ahci_devices[100];
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uint32_t count_ahci_devices = 0;
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/**
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* @brief 初始化ahci模块
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*
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*/
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void ahci_init()
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{
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pci_get_device_structure(0x1, 0x6, ahci_devices, &count_ahci_devices);
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for(int i=0;i<count_ahci_devices;++i)
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{
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kdebug("[%d] class_code=%d, sub_class=%d, progIF=%d", i, ahci_devices[i]->Class_code, ahci_devices[i]->SubClass, ahci_devices[i]->ProgIF);
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}
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}
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@ -1,6 +1,7 @@
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#pragma once
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#pragma once
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#include "../block_device.h"
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#include "../block_device.h"
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#include "../../pci/pci.h"
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/**
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/**
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* @brief 在SATA3.0规范中定义的Frame Information Structure类型
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* @brief 在SATA3.0规范中定义的Frame Information Structure类型
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@ -177,6 +178,28 @@ typedef struct tagFIS_DMA_SETUP
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} FIS_DMA_SETUP;
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} FIS_DMA_SETUP;
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typedef volatile struct tagHBA_PORT
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{
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uint32_t clb; // 0x00, command list base address, 1K-byte aligned
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uint32_t clbu; // 0x04, command list base address upper 32 bits
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uint32_t fb; // 0x08, FIS base address, 256-byte aligned
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uint32_t fbu; // 0x0C, FIS base address upper 32 bits
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uint32_t is; // 0x10, interrupt status
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uint32_t ie; // 0x14, interrupt enable
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uint32_t cmd; // 0x18, command and status
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uint32_t rsv0; // 0x1C, Reserved
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uint32_t tfd; // 0x20, task file data
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uint32_t sig; // 0x24, signature
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uint32_t ssts; // 0x28, SATA status (SCR0:SStatus)
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uint32_t sctl; // 0x2C, SATA control (SCR2:SControl)
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uint32_t serr; // 0x30, SATA error (SCR1:SError)
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uint32_t sact; // 0x34, SATA active (SCR3:SActive)
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uint32_t ci; // 0x38, command issue
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uint32_t sntf; // 0x3C, SATA notification (SCR4:SNotification)
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uint32_t fbs; // 0x40, FIS-based switch control
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uint32_t rsv1[11]; // 0x44 ~ 0x6F, Reserved
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uint32_t vendor[4]; // 0x70 ~ 0x7F, vendor specific
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} HBA_PORT;
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typedef volatile struct tagHBA_MEM
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typedef volatile struct tagHBA_MEM
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{
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{
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// 0x00 - 0x2B, Generic Host Control
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// 0x00 - 0x2B, Generic Host Control
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@ -202,28 +225,6 @@ typedef volatile struct tagHBA_MEM
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HBA_PORT ports[1]; // 1 ~ 32
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HBA_PORT ports[1]; // 1 ~ 32
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} HBA_MEM;
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} HBA_MEM;
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typedef volatile struct tagHBA_PORT
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{
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uint32_t clb; // 0x00, command list base address, 1K-byte aligned
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uint32_t clbu; // 0x04, command list base address upper 32 bits
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uint32_t fb; // 0x08, FIS base address, 256-byte aligned
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uint32_t fbu; // 0x0C, FIS base address upper 32 bits
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uint32_t is; // 0x10, interrupt status
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uint32_t ie; // 0x14, interrupt enable
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uint32_t cmd; // 0x18, command and status
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uint32_t rsv0; // 0x1C, Reserved
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uint32_t tfd; // 0x20, task file data
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uint32_t sig; // 0x24, signature
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uint32_t ssts; // 0x28, SATA status (SCR0:SStatus)
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uint32_t sctl; // 0x2C, SATA control (SCR2:SControl)
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uint32_t serr; // 0x30, SATA error (SCR1:SError)
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uint32_t sact; // 0x34, SATA active (SCR3:SActive)
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uint32_t ci; // 0x38, command issue
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uint32_t sntf; // 0x3C, SATA notification (SCR4:SNotification)
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uint32_t fbs; // 0x40, FIS-based switch control
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uint32_t rsv1[11]; // 0x44 ~ 0x6F, Reserved
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uint32_t vendor[4]; // 0x70 ~ 0x7F, vendor specific
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} HBA_PORT;
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// There are four kinds of FIS which may be sent to the host by the device as indicated in the following structure declaration.
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// There are four kinds of FIS which may be sent to the host by the device as indicated in the following structure declaration.
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//
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//
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@ -279,6 +280,19 @@ typedef struct tagHBA_CMD_HEADER
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uint32_t rsv1[4]; // Reserved
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uint32_t rsv1[4]; // Reserved
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} HBA_CMD_HEADER;
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} HBA_CMD_HEADER;
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typedef struct tagHBA_PRDT_ENTRY
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{
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uint32_t dba; // Data base address
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uint32_t dbau; // Data base address upper 32 bits
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uint32_t rsv0; // Reserved
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// DW3
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uint32_t dbc:22; // Byte count, 4M max
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uint32_t rsv1:9; // Reserved
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uint32_t i:1; // Interrupt on completion
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} HBA_PRDT_ENTRY;
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typedef struct tagHBA_CMD_TBL
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typedef struct tagHBA_CMD_TBL
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{
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{
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// 0x00
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// 0x00
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@ -294,24 +308,38 @@ typedef struct tagHBA_CMD_TBL
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HBA_PRDT_ENTRY prdt_entry[1]; // Physical region descriptor table entries, 0 ~ 65535
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HBA_PRDT_ENTRY prdt_entry[1]; // Physical region descriptor table entries, 0 ~ 65535
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} HBA_CMD_TBL;
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} HBA_CMD_TBL;
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typedef struct tagHBA_PRDT_ENTRY
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{
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uint32_t dba; // Data base address
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#define SATA_SIG_ATA 0x00000101 // SATA drive
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uint32_t dbau; // Data base address upper 32 bits
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#define SATA_SIG_ATAPI 0xEB140101 // SATAPI drive
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uint32_t rsv0; // Reserved
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#define SATA_SIG_SEMB 0xC33C0101 // Enclosure management bridge
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#define SATA_SIG_PM 0x96690101 // Port multiplier
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// DW3
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#define AHCI_DEV_NULL 0
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uint32_t dbc:22; // Byte count, 4M max
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#define AHCI_DEV_SATA 1
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uint32_t rsv1:9; // Reserved
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#define AHCI_DEV_SEMB 2
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uint32_t i:1; // Interrupt on completion
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#define AHCI_DEV_PM 3
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} HBA_PRDT_ENTRY;
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#define AHCI_DEV_SATAPI 4
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#define HBA_PORT_IPM_ACTIVE 1
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#define HBA_PORT_DET_PRESENT 3
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struct block_device_request_queue ahci_req_queue;
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struct block_device_request_queue ahci_req_queue;
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/*
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struct block_device_operation ahci_operation =
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struct block_device_operation ahci_operation =
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{
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{
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.open = ahci_open,
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.open = ahci_open,
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.close = ahci_close,
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.close = ahci_close,
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.ioctl = ahci_ioctl,
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.ioctl = ahci_ioctl,
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.transfer = ahci_transfer,
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.transfer = ahci_transfer,
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};
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};
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*/
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/**
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* @brief 初始化ahci模块
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*
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*/
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void ahci_init();
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@ -436,7 +436,7 @@ void pci_checkAllBuses()
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void pci_init()
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void pci_init()
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{
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{
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kinfo("Initializing PCI bus!");
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kinfo("Initializing PCI bus...");
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pci_checkAllBuses();
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pci_checkAllBuses();
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kinfo("Total pci device and function num = %d", count_device_list);
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kinfo("Total pci device and function num = %d", count_device_list);
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@ -531,7 +531,7 @@ int pci_enable_msi(void *header, uint8_t vector, uint32_t processor, uint8_t edg
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pci_write_config(ptr->bus, ptr->device, ptr->func, cap_ptr, tmp);
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pci_write_config(ptr->bus, ptr->device, ptr->func, cap_ptr, tmp);
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break;
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break;
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case 0x01: // pci to pci bridge
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case 0x01: // pci to pci bridge
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if (!(ptr->Status & 0x10))
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if (!(ptr->Status & 0x10))
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return E_NOT_SUPPORT_MSI;
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return E_NOT_SUPPORT_MSI;
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@ -574,4 +574,32 @@ int pci_enable_msi(void *header, uint8_t vector, uint32_t processor, uint8_t edg
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}
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}
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return 0;
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return 0;
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}
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/**
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* @brief 获取 device structure
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*
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* @param class_code
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* @param sub_class
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* @param res 返回的结果数组
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*/
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void pci_get_device_structure(uint8_t class_code, uint8_t sub_class, struct pci_device_structure_header_t *res[], uint32_t *count_res)
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{
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struct pci_device_structure_header_t *ptr_begin = container_of(pci_device_structure_list, struct pci_device_structure_header_t, list);
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struct pci_device_structure_header_t *ptr = container_of(pci_device_structure_list, struct pci_device_structure_header_t, list);
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*count_res = 0;
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for (int i = 0; i < count_device_list; ++i)
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{
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if ((ptr->Class_code == 1) && (ptr->SubClass == 6))
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{
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kdebug("[%d] class_code=%d, sub_class=%d, progIF=%d", i, ptr->Class_code, ptr->SubClass, ptr->ProgIF);
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res[*count_res] = ptr;
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++(*count_res);
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}
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ptr = container_of(list_next(&(ptr->list)), struct pci_device_structure_header_t, list);
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}
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}
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}
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@ -216,4 +216,13 @@ void pci_checkAllBuses();
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*
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*
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* @return 返回码
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* @return 返回码
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*/
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*/
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int pci_enable_msi(void * header, uint8_t vector, uint32_t processor, uint8_t edge_trigger, uint8_t assert);
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int pci_enable_msi(void * header, uint8_t vector, uint32_t processor, uint8_t edge_trigger, uint8_t assert);
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/**
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* @brief 获取 device structure
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*
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* @param class_code
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* @param sub_class
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* @param res 返回的结果数组
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*/
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void pci_get_device_structure(uint8_t class_code, uint8_t sub_class, struct pci_device_structure_header_t* res[], uint32_t* count_res);
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@ -19,6 +19,7 @@
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#include "driver/mouse/ps2_mouse.h"
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#include "driver/mouse/ps2_mouse.h"
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#include "driver/disk/ata.h"
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#include "driver/disk/ata.h"
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#include "driver/pci/pci.h"
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#include "driver/pci/pci.h"
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#include "driver/disk/ahci/ahci.h"
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unsigned int *FR_address = (unsigned int *)0xb8000; //帧缓存区的地址
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unsigned int *FR_address = (unsigned int *)0xb8000; //帧缓存区的地址
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@ -168,6 +169,7 @@ void system_initialize()
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//ps2_mouse_init();
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//ps2_mouse_init();
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ata_init();
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ata_init();
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pci_init();
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pci_init();
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ahci_init();
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// test_slab();
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// test_slab();
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// test_mm();
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// test_mm();
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Reference in New Issue
Block a user