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https://github.com/DragonOS-Community/DragonOS.git
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更改xhci驱动程序对寄存器的读写范围。
This commit is contained in:
fslongjin
parent
33a1e2baad
commit
7d983bd5cb
@ -69,49 +69,44 @@ hardware_intr_controller xhci_hc_intr_controller =
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这种情况下，我们必须从32bit的寄存器的0地址处开始读取32bit，然后通过移位的方式得到其中的字节。
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*/
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#define xhci_read_cap_reg32(id, offset) (*(uint32_t *)(xhci_hc[id].vbase + (offset)))
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#define xhci_read_cap_reg32(id, offset) (__read4b(xhci_hc[id].vbase + (offset)))
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#define xhci_get_ptr_cap_reg32(id, offset) ((uint32_t *)(xhci_hc[id].vbase + (offset)))
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#define xhci_write_cap_reg32(id, offset, value) (*(uint32_t *)(xhci_hc[id].vbase + (offset)) = (uint32_t)(value))
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#define xhci_write_cap_reg32(id, offset, value) (__write4b(xhci_hc[id].vbase + (offset), (value)))
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#define xhci_read_cap_reg64(id, offset) (*(uint64_t *)(xhci_hc[id].vbase + (offset)))
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#define xhci_read_cap_reg64(id, offset) (__read8b(xhci_hc[id].vbase + (offset)))
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#define xhci_get_ptr_reg64(id, offset) ((uint64_t *)(xhci_hc[id].vbase + (offset)))
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#define xhci_write_cap_reg64(id, offset, value) (*(uint64_t *)(xhci_hc[id].vbase + (offset)) = (uint64_t)(value))
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#define xhci_write_cap_reg64(id, offset, value) (__write8b(xhci_hc[id].vbase + (offset), (value)))
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#define xhci_read_op_reg8(id, offset) (*(uint8_t *)(xhci_hc[id].vbase_op + (offset)))
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#define xhci_get_ptr_op_reg8(id, offset) ((uint8_t *)(xhci_hc[id].vbase_op + (offset)))
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#define xhci_write_op_reg8(id, offset, value) (*(uint8_t *)(xhci_hc[id].vbase_op + (offset)) = (uint8_t)(value))
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#define xhci_read_op_reg32(id, offset) (*(uint32_t *)(xhci_hc[id].vbase_op + (offset)))
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#define xhci_read_op_reg32(id, offset) (__read4b(xhci_hc[id].vbase_op + (offset)))
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#define xhci_get_ptr_op_reg32(id, offset) ((uint32_t *)(xhci_hc[id].vbase_op + (offset)))
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#define xhci_write_op_reg32(id, offset, value) (*(uint32_t *)(xhci_hc[id].vbase_op + (offset)) = (uint32_t)(value))
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#define xhci_write_op_reg32(id, offset, value) (__write4b(xhci_hc[id].vbase_op + (offset), (value)))
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#define xhci_read_op_reg64(id, offset) (*(uint64_t *)(xhci_hc[id].vbase_op + (offset)))
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#define xhci_read_op_reg64(id, offset) (__read8b(xhci_hc[id].vbase_op + (offset)))
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#define xhci_get_ptr_op_reg64(id, offset) ((uint64_t *)(xhci_hc[id].vbase_op + (offset)))
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#define xhci_write_op_reg64(id, offset, value) (*(uint64_t *)(xhci_hc[id].vbase_op + (offset)) = (uint64_t)(value))
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#define xhci_write_mem32(vaddr, value) (*(uint32_t *)(vaddr) = (value))
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#define xhci_write_mem64(vaddr, value) (*(uint64_t *)(vaddr) = (value))
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#define xhci_read_mem32(vaddr) (*(uint32_t *)(vaddr))
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#define xhci_read_mem64(vaddr) (*(uint64_t *)(vaddr))
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#define xhci_write_op_reg64(id, offset, value) (__write8b(xhci_hc[id].vbase_op + (offset), (value)))
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/**
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* @brief 计算中断寄存器组虚拟地址
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* @param id 主机控制器id
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* @param num xhci中断寄存器组号
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*/
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#define xhci_calc_intr_vaddr(id, num) (xhci_hc[id].vbase + xhci_hc[id].rts_offset + XHCI_RT_IR0 + num * XHCI_IR_SIZE)
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#define xhci_calc_intr_vaddr(id, num) (xhci_hc[id].vbase + xhci_hc[id].rts_offset + XHCI_RT_IR0 + (num)*XHCI_IR_SIZE)
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/**
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* @brief 读取/写入中断寄存器
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* @param id 主机控制器id
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* @param num xhci中断寄存器组号
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* @param intr_offset 寄存器在当前寄存器组中的偏移量
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*/
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#define xhci_read_intr_reg32(id, num, intr_offset) (*(uint32_t *)(xhci_calc_intr_vaddr(id, num) + intr_offset))
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#define xhci_write_intr_reg32(id, num, intr_offset, value) (*(uint32_t *)(xhci_calc_intr_vaddr(id, num) + intr_offset) = value)
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#define xhci_read_intr_reg64(id, num, intr_offset) (*(uint64_t *)(xhci_calc_intr_vaddr(id, num) + intr_offset))
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#define xhci_write_intr_reg64(id, num, intr_offset, value) (*(uint64_t *)(xhci_calc_intr_vaddr(id, num) + intr_offset) = value)
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#define xhci_read_intr_reg32(id, num, intr_offset) (__read4b(xhci_calc_intr_vaddr(id, num) + (intr_offset)))
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#define xhci_write_intr_reg32(id, num, intr_offset, value) (__write4b(xhci_calc_intr_vaddr(id, num) + (intr_offset), (value)))
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#define xhci_read_intr_reg64(id, num, intr_offset) (__read8b(xhci_calc_intr_vaddr(id, num) + (intr_offset)))
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#define xhci_write_intr_reg64(id, num, intr_offset, value) (__write8b(xhci_calc_intr_vaddr(id, num) + (intr_offset), (value)))
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#define xhci_is_aligned64(addr) ((addr & 0x3f) == 0) // 是否64bytes对齐
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#define xhci_is_aligned64(addr) (((addr)&0x3f) == 0) // 是否64bytes对齐
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/**
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* @brief 判断端口信息
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@ -172,9 +167,9 @@ static int xhci_hc_find_available_id()
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*/
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static __always_inline void xhci_get_trb(struct xhci_TRB_t *trb, const uint64_t address)
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{
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trb->param = xhci_read_mem64(address);
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trb->status = xhci_read_mem32(address + 8);
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trb->command = xhci_read_mem32(address + 12);
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trb->param = __read8b(address);
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trb->status = __read4b(address + 8);
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trb->command = __read4b(address + 12);
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}
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/**
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@ -185,9 +180,9 @@ static __always_inline void xhci_get_trb(struct xhci_TRB_t *trb, const uint64_t
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*/
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static __always_inline void xhci_set_trb(struct xhci_TRB_t *trb, const uint64_t address)
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{
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xhci_write_mem64(address, trb->param);
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xhci_write_mem32(address + 8, trb->status);
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xhci_write_mem32(address + 12, trb->command);
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__write8b(address, trb->param);
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__write4b(address + 8, trb->status);
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__write4b(address + 12, trb->command);
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}
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/**
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@ -781,7 +776,7 @@ void xhci_hc_irq_handler(uint64_t irq_num, uint64_t cid, struct pt_regs *regs)
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{
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case TRB_TYPE_TRANS_EVENT: // 当前 event trb是 transfer event TRB
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// If SPD was encountered in this TD, comp_code will be SPD, else it should be SUCCESS (specs 4.10.1.1)
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xhci_write_mem32(phys_2_virt(event_trb.param), (event_trb.status | XHCI_IRQ_DONE)); // return code + bytes *not* transferred
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__write4b((uint64_t)phys_2_virt(event_trb.param), (event_trb.status | XHCI_IRQ_DONE)); // return code + bytes *not* transferred
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break;
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default:
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@ -841,6 +836,7 @@ static int xhci_reset_port(const int id, const int port)
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io_mfence();
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// 确保端口的status被清0
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xhci_write_op_reg32(id, port_status_offset + XHCI_PORT_PORTSC, (1 << 9) | XHCI_PORTUSB_CHANGE_BITS);
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// kdebug("to reset timeout;");
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io_mfence();
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// 重置当前端口
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if (XHCI_PORT_IS_USB3(id, port))
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@ -849,13 +845,14 @@ static int xhci_reset_port(const int id, const int port)
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xhci_write_op_reg32(id, port_status_offset + XHCI_PORT_PORTSC, (1 << 9) | (1 << 4));
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retval = -ETIMEDOUT;
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// kdebug("to wait reset timeout;");
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// 等待portsc的port reset change位被置位，说明reset完成
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int timeout = 200;
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while (timeout)
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{
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io_mfence();
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uint32_t val = xhci_read_op_reg32(id, port_status_offset + XHCI_PORT_PORTSC);
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// kdebug("val=%#010lx", val);
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io_mfence();
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if (XHCI_PORT_IS_USB3(id, port) && (val & (1 << 31)) == 0)
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break;
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@ -872,13 +869,15 @@ static int xhci_reset_port(const int id, const int port)
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if (timeout > 0)
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{
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// 等待恢复
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usleep(USB_TIME_RST_REC * 1000);
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usleep(USB_TIME_RST_REC * 100);
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// kdebug("to check if reset ok");
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uint32_t val = xhci_read_op_reg32(id, port_status_offset + XHCI_PORT_PORTSC);
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io_mfence();
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// 如果reset之后，enable bit仍然是1，那么说明reset成功
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if (val & (1 << 1))
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{
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// kdebug("reset ok");
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retval = 0;
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io_mfence();
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// 清除status change bit
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@ -888,7 +887,7 @@ static int xhci_reset_port(const int id, const int port)
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else
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retval = -1;
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}
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// kdebug("reset ok!");
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// 如果usb2端口成功reset，则处理该端口的active状态
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if (retval == 0 && XHCI_PORT_IS_USB2(id, port))
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{
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@ -928,7 +927,7 @@ static uint64_t xhci_initialize_slot(const int id, const int slot_id, const int
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uint64_t device_context_vaddr = (uint64_t)kzalloc(xhci_hc[id].context_size * 2, 0);
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// kdebug("slot id=%d, device_context_vaddr=%#018lx, port=%d", slot_id, device_context_vaddr, port);
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// 写到数组中
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xhci_write_mem64(xhci_hc[id].dcbaap_vaddr + (slot_id * sizeof(uint64_t)), virt_2_phys(device_context_vaddr));
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__write8b(xhci_hc[id].dcbaap_vaddr + (slot_id * sizeof(uint64_t)), virt_2_phys(device_context_vaddr));
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slot_ctx.entries = 1;
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slot_ctx.speed = speed;
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@ -1009,7 +1008,7 @@ static int xhci_set_address(const int id, const uint64_t slot_vaddr, const int s
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uint64_t input_ctx_buffer = (uint64_t)kzalloc(xhci_hc[id].context_size * 32, 0);
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// 置位input control context和slot context的add bit
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xhci_write_mem32(input_ctx_buffer + 4, 0x3);
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__write4b(input_ctx_buffer + 4, 0x3);
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// 拷贝slot上下文和control ep上下文到输入上下文中
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__write_slot(input_ctx_buffer + xhci_hc[id].context_size, (struct xhci_slot_context_t *)slot_vaddr);
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@ -1198,9 +1197,9 @@ static int xhci_wait_for_interrupt(const int id, uint64_t status_vaddr)
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int timer = 500;
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while (timer)
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{
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if (xhci_read_mem32(status_vaddr) & XHCI_IRQ_DONE)
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if (__read4b(status_vaddr) & XHCI_IRQ_DONE)
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{
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uint32_t status = xhci_read_mem32(status_vaddr);
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uint32_t status = __read4b(status_vaddr);
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// 判断完成码
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switch (xhci_get_comp_code(status))
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{
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@ -1349,15 +1348,17 @@ static int xhci_get_descriptor(const int id, const int port_id)
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break;
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}
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}
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kdebug("to init slot");
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// 初始化接口的上下文
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uint64_t slot_vaddr = xhci_initialize_slot(id, slot_id, port_id, speed, max_packet);
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kdebug("to set address");
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// 发送 address_device命令
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retval = xhci_set_address(id, slot_vaddr, slot_id, true);
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if (retval != 0)
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return retval;
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kdebug("to ctrl in");
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// 发送用于 “get_descriptor” 的数据包。
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count = xhci_control_in(id, &dev_desc, 8, slot_id, max_packet);
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if (unlikely(count == 0))
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@ -1370,13 +1371,16 @@ static int xhci_get_descriptor(const int id, const int port_id)
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*/
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// 重置当前端口
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kdebug("to reset");
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xhci_reset_port(id, port_id);
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// 再次发送 set_address命令
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kdebug("to set addr again");
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retval = xhci_set_address(id, slot_vaddr, slot_id, false);
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if (retval != 0)
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return retval;
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kdebug("to ctrl in again");
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count = xhci_control_in(id, &dev_desc, 18, slot_id, max_packet);
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if (unlikely(count == 0))
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return -EAGAIN;
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@ -1441,10 +1445,12 @@ static int xhci_hc_start_ports(int id)
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{
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if (XHCI_PORT_IS_USB2(id, i) && XHCI_PORT_IS_ACTIVE(id, i))
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{
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// kdebug("initializing usb2: %d", i);
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// reset该端口
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if (likely(xhci_reset_port(id, i) == 0)) // 如果端口reset成功，就获取它的描述符
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// 否则，reset函数会把它给设置为未激活，并且标志配对的usb2端口是激活的
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{
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// kdebug("reset ok");
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if (xhci_get_descriptor(id, i) == 0)
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++cnt;
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else
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@ -1537,9 +1543,9 @@ static int xhci_send_command(int id, struct xhci_TRB_t *trb, const bool do_ring)
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uint64_t origin_trb_vaddr = xhci_hc[id].cmd_trb_vaddr;
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// 必须先写入参数和状态数据，最后写入command
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xhci_write_mem64(xhci_hc[id].cmd_trb_vaddr, trb->param); // 参数
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xhci_write_mem32(xhci_hc[id].cmd_trb_vaddr + 8, trb->status); // 状态
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xhci_write_mem32(xhci_hc[id].cmd_trb_vaddr + 12, trb->command | xhci_hc[id].cmd_trb_cycle); // 命令
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__write8b(xhci_hc[id].cmd_trb_vaddr, trb->param); // 参数
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__write4b(xhci_hc[id].cmd_trb_vaddr + 8, trb->status); // 状态
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__write4b(xhci_hc[id].cmd_trb_vaddr + 12, trb->command | xhci_hc[id].cmd_trb_cycle); // 命令
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xhci_hc[id].cmd_trb_vaddr += sizeof(struct xhci_TRB_t); // 跳转到下一个trb
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@ -1564,7 +1570,7 @@ static int xhci_send_command(int id, struct xhci_TRB_t *trb, const bool do_ring)
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// Now wait for the interrupt to happen
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// We use bit 31 of the command dword since it is reserved
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while (timer && ((xhci_read_mem32(origin_trb_vaddr + 8) & XHCI_IRQ_DONE) == 0))
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while (timer && ((__read4b(origin_trb_vaddr + 8) & XHCI_IRQ_DONE) == 0))
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{
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usleep(1000);
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--timer;
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