riscv: 完成UEFI初始化,能正确设置memblock的信息 (#501)

* riscv: 完成UEFI初始化,能正确设置memblock的信息

* sbi增加reset功能

* 把虚拟CPU修改为sifive-u54,使qemu能更正确地模拟硬件行为

* 修复内存页面映射未设置“DIRTY”、”ACCESSED“、”GLOBAL“位,导致真机page fault的问题
This commit is contained in:
LoGin
2024-01-26 18:08:39 +08:00
committed by GitHub
parent a381e482cb
commit 9284987850
22 changed files with 754 additions and 130 deletions

View File

@ -17,9 +17,9 @@
#define SR_VS 0x00000600
#define SR_FS_VS (SR_FS | SR_VS) /* Vector and Floating-Point Unit */
#define SATP_MODE_39 0x8000000000000000UL
#define SATP_MODE_48 0x9000000000000000UL
#define SATP_MODE_57 0xa000000000000000UL
#define SATP_MODE_39 0x8000000000000000ULL
#define SATP_MODE_48 0x9000000000000000ULL
#define SATP_MODE_57 0xa000000000000000ULL
#define PAGE_OFFSET 0xffffffc000000000
#define KERNEL_LINK_OFFSET 0x1000000
@ -84,7 +84,6 @@ ENTRY(_start)
call initial_map_1g_identical
__init_set_pgtable_loop_end:
call __initial_reloacate_enable_mmu
.option push
@ -119,6 +118,7 @@ __initial_reloacate_enable_mmu:
//
la t0, __initial_start_load_paddr
ld t0, 0(t0)
li t1, KERNEL_VIRT_START
sub t1, t1, t0
@ -128,18 +128,27 @@ __initial_reloacate_enable_mmu:
/* Point stvec to virtual address of intruction after satp write */
/* Set trap vector to spin forever to help debug */
la a2, __initial_Lsecondary_park
la a2, 1f
add a2, a2, t1
csrw CSR_TVEC, a2
// enable MMU
la a2, __initial_pgtable
srli a2, a2, 12
la a0, __initial_satp_mode
ld a0, 0(a0)
or a2, a2, a0
sfence.vma
csrw satp, a2
1:
la a0, __initial_Lsecondary_park
add a0, a0, t1
csrw CSR_TVEC, a0
csrw satp, a2
sfence.vma
ret
@ -165,7 +174,7 @@ initial_map_256M_phys_addr:
and t2, t2, t1
// L0
srl t2, t2, 30
srli t2, t2, 30
andi t2, t2, 511
@ -220,7 +229,7 @@ __initial_set_l1_pgtable_loop:
li t1, 0x3FFFFFFFFFFFFF
and t3, t3, t1 // t3 = t3 & 0x3FFFFFFFFFFFFF
slli t3, t3, 10 // t3 = t3 << 10
ori t3, t3, 0xf // L1R/W/X/V = 1
ori t3, t3, 0xEF // L1set R/W/X/V/A/D/G = 1
// L1
sd t3, 0(t0)
@ -262,41 +271,55 @@ initial_map_1g_identical:
// ,t0
and t0, t0, a0
// t2
mv t2, a1
// 1g
li t1, -0x40000000
and t2, t2, t1
// 30L0
srl t2, t2, 30
srli t2, t2, 30
// 511L0
andi t2, t2, 511
//
// li t2, 0xf // , R/W/X/V = 1
la t4, __initial_pgtable
slli t3, t2, 3 // t3 = t2 * 8
add t4, t4, t3 // t4 = t4 + t3
mv t3, t0
srli t3, t3, 12 // t3 = t0 >> 12 (page frame number)
slli t3, t3, 10 // t3 = t3 << 10
ori t3, t3, 0xf // set R/W/X/V = 1
// t0L0
ori t3, t3, 0xEF // set R/W/X/V/A/D/G = 1
// deltapfn
li t2, 0x40000000
srli t2, t2, 12
// delta pfn10
slli t2, t2, 10
li t1, 2
__loop_set_8g:
sd t3, 0(t4)
// t4
addi t4, t4, 8
// t3 (1G)
li t2, 0x40000000
// 1Gpfn
add t3, t3, t2
sd t3, 0(t4)
addi t1, t1, -1
bnez t1, __loop_set_8g
ret
//
//
// a0: page table address