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🆕 ahci的FIS数据结构
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fslongjin
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de7583cf31
3
kernel/driver/disk/ahci/ahci.c
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3
kernel/driver/disk/ahci/ahci.c
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#include "ahci.h"
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#include "../../../common/kprint.h"
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262
kernel/driver/disk/ahci/ahci.h
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kernel/driver/disk/ahci/ahci.h
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#pragma once
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#include "../block_device.h"
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/**
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* @brief 在SATA3.0规范中定义的Frame Information Structure类型
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*
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*/
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typedef enum
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{
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FIS_TYPE_REG_H2D = 0x27, // Register FIS - host to device
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FIS_TYPE_REG_D2H = 0x34, // Register FIS - device to host
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FIS_TYPE_DMA_ACT = 0x39, // DMA activate FIS - device to host
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FIS_TYPE_DMA_SETUP = 0x41, // DMA setup FIS - bidirectional
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FIS_TYPE_DATA = 0x46, // Data FIS - bidirectional
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FIS_TYPE_BIST = 0x58, // BIST activate FIS - bidirectional
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FIS_TYPE_PIO_SETUP = 0x5F, // PIO setup FIS - device to host
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FIS_TYPE_DEV_BITS = 0xA1, // Set device bits FIS - device to host
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} FIS_TYPE;
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/**
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* @brief FIS_REG_H2D 被用于从主机向设备发送控制命令
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* 注意：reserved bit应当被清零
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*/
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typedef struct tagFIS_REG_H2D
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{
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// DWORD 0
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uint8_t fis_type; // FIS_TYPE_REG_H2D
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uint8_t pmport : 4; // Port multiplier
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uint8_t rsv0 : 3; // Reserved
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uint8_t c : 1; // 1: Command, 0: Control
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uint8_t command; // Command register
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uint8_t featurel; // Feature register, 7:0
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// DWORD 1
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uint8_t lba0; // LBA low register, 7:0
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uint8_t lba1; // LBA mid register, 15:8
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uint8_t lba2; // LBA high register, 23:16
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uint8_t device; // Device register
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// DWORD 2
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uint8_t lba3; // LBA register, 31:24
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uint8_t lba4; // LBA register, 39:32
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uint8_t lba5; // LBA register, 47:40
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uint8_t featureh; // Feature register, 15:8
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// DWORD 3
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uint8_t countl; // Count register, 7:0
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uint8_t counth; // Count register, 15:8
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uint8_t icc; // Isochronous command completion
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uint8_t control; // Control register
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// DWORD 4
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uint8_t rsv1[4]; // Reserved
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} FIS_REG_H2D;
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// A device to host register FIS is used by the device to notify the host that some ATA register has changed.
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// It contains the updated task files such as status, error and other registers.
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typedef struct tagFIS_REG_D2H
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{
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// DWORD 0
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uint8_t fis_type; // FIS_TYPE_REG_D2H
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uint8_t pmport : 4; // Port multiplier
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uint8_t rsv0 : 2; // Reserved
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uint8_t i : 1; // Interrupt bit
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uint8_t rsv1 : 1; // Reserved
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uint8_t status; // Status register
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uint8_t error; // Error register
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// DWORD 1
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uint8_t lba0; // LBA low register, 7:0
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uint8_t lba1; // LBA mid register, 15:8
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uint8_t lba2; // LBA high register, 23:16
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uint8_t device; // Device register
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// DWORD 2
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uint8_t lba3; // LBA register, 31:24
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uint8_t lba4; // LBA register, 39:32
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uint8_t lba5; // LBA register, 47:40
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uint8_t rsv2; // Reserved
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// DWORD 3
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uint8_t countl; // Count register, 7:0
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uint8_t counth; // Count register, 15:8
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uint8_t rsv3[2]; // Reserved
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// DWORD 4
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uint8_t rsv4[4]; // Reserved
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} FIS_REG_D2H;
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// This FIS is used by the host or device to send data payload. The data size can be varied.
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typedef struct tagFIS_DATA
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{
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// DWORD 0
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uint8_t fis_type; // FIS_TYPE_DATA
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uint8_t pmport : 4; // Port multiplier
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uint8_t rsv0 : 4; // Reserved
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uint8_t rsv1[2]; // Reserved
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// DWORD 1 ~ N
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uint32_t data[1]; // Payload
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} FIS_DATA;
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// This FIS is used by the device to tell the host that it’s about to send or ready to receive a PIO data payload.
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typedef struct tagFIS_PIO_SETUP
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{
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// DWORD 0
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uint8_t fis_type; // FIS_TYPE_PIO_SETUP
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uint8_t pmport : 4; // Port multiplier
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uint8_t rsv0 : 1; // Reserved
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uint8_t d : 1; // Data transfer direction, 1 - device to host
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uint8_t i : 1; // Interrupt bit
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uint8_t rsv1 : 1;
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uint8_t status; // Status register
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uint8_t error; // Error register
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// DWORD 1
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uint8_t lba0; // LBA low register, 7:0
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uint8_t lba1; // LBA mid register, 15:8
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uint8_t lba2; // LBA high register, 23:16
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uint8_t device; // Device register
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// DWORD 2
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uint8_t lba3; // LBA register, 31:24
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uint8_t lba4; // LBA register, 39:32
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uint8_t lba5; // LBA register, 47:40
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uint8_t rsv2; // Reserved
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// DWORD 3
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uint8_t countl; // Count register, 7:0
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uint8_t counth; // Count register, 15:8
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uint8_t rsv3; // Reserved
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uint8_t e_status; // New value of status register
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// DWORD 4
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uint16_t tc; // Transfer count
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uint8_t rsv4[2]; // Reserved
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} FIS_PIO_SETUP;
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typedef struct tagFIS_DMA_SETUP
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{
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// DWORD 0
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uint8_t fis_type; // FIS_TYPE_DMA_SETUP
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uint8_t pmport : 4; // Port multiplier
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uint8_t rsv0 : 1; // Reserved
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uint8_t d : 1; // Data transfer direction, 1 - device to host
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uint8_t i : 1; // Interrupt bit
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uint8_t a : 1; // Auto-activate. Specifies if DMA Activate FIS is needed
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uint8_t rsved[2]; // Reserved
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// DWORD 1&2
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uint64_t DMAbufferID; // DMA Buffer Identifier. Used to Identify DMA buffer in host memory.
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// SATA Spec says host specific and not in Spec. Trying AHCI spec might work.
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// DWORD 3
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uint32_t rsvd; // More reserved
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// DWORD 4
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uint32_t DMAbufOffset; // Byte offset into buffer. First 2 bits must be 0
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// DWORD 5
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uint32_t TransferCount; // Number of bytes to transfer. Bit 0 must be 0
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// DWORD 6
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uint32_t resvd; // Reserved
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} FIS_DMA_SETUP;
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typedef volatile struct tagHBA_MEM
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{
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// 0x00 - 0x2B, Generic Host Control
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uint32_t cap; // 0x00, Host capability
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uint32_t ghc; // 0x04, Global host control
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uint32_t is; // 0x08, Interrupt status
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uint32_t pi; // 0x0C, Port implemented
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uint32_t vs; // 0x10, Version
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uint32_t ccc_ctl; // 0x14, Command completion coalescing control
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uint32_t ccc_pts; // 0x18, Command completion coalescing ports
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uint32_t em_loc; // 0x1C, Enclosure management location
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uint32_t em_ctl; // 0x20, Enclosure management control
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uint32_t cap2; // 0x24, Host capabilities extended
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uint32_t bohc; // 0x28, BIOS/OS handoff control and status
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// 0x2C - 0x9F, Reserved
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uint8_t rsv[0xA0-0x2C];
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// 0xA0 - 0xFF, Vendor specific registers
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uint8_t vendor[0x100-0xA0];
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// 0x100 - 0x10FF, Port control registers
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HBA_PORT ports[1]; // 1 ~ 32
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} HBA_MEM;
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typedef volatile struct tagHBA_PORT
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{
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uint32_t clb; // 0x00, command list base address, 1K-byte aligned
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uint32_t clbu; // 0x04, command list base address upper 32 bits
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uint32_t fb; // 0x08, FIS base address, 256-byte aligned
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uint32_t fbu; // 0x0C, FIS base address upper 32 bits
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uint32_t is; // 0x10, interrupt status
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uint32_t ie; // 0x14, interrupt enable
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uint32_t cmd; // 0x18, command and status
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uint32_t rsv0; // 0x1C, Reserved
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uint32_t tfd; // 0x20, task file data
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uint32_t sig; // 0x24, signature
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uint32_t ssts; // 0x28, SATA status (SCR0:SStatus)
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uint32_t sctl; // 0x2C, SATA control (SCR2:SControl)
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uint32_t serr; // 0x30, SATA error (SCR1:SError)
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uint32_t sact; // 0x34, SATA active (SCR3:SActive)
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uint32_t ci; // 0x38, command issue
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uint32_t sntf; // 0x3C, SATA notification (SCR4:SNotification)
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uint32_t fbs; // 0x40, FIS-based switch control
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uint32_t rsv1[11]; // 0x44 ~ 0x6F, Reserved
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uint32_t vendor[4]; // 0x70 ~ 0x7F, vendor specific
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} HBA_PORT;
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// There are four kinds of FIS which may be sent to the host by the device as indicated in the following structure declaration.
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//
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typedef volatile struct tagHBA_FIS
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{
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// 0x00
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FIS_DMA_SETUP dsfis; // DMA Setup FIS
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uint8_t pad0[4];
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// 0x20
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FIS_PIO_SETUP psfis; // PIO Setup FIS
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uint8_t pad1[12];
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// 0x40
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FIS_REG_D2H rfis; // Register – Device to Host FIS
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uint8_t pad2[4];
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// 0x58
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//FIS_DEV_BITS sdbfis; // Set Device Bit FIS
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// 0x60
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uint8_t ufis[64];
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// 0xA0
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uint8_t rsv[0x100-0xA0];
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} HBA_FIS;
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struct block_device_request_queue ahci_req_queue;
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struct block_device_operation ahci_operation =
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{
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.open = ahci_open,
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.close = ahci_close,
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.ioctl = ahci_ioctl,
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.transfer = ahci_transfer,
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};
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@ -56,8 +56,7 @@ void ps2_keyboard_handler(ul irq_num, ul param, struct pt_regs *regs)
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*/
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void ps2_keyboard_init()
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{
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// 开启键盘中断，中断向量号为0x21，物理模式，投递至BSP处理器
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apic_ioapic_write_rte(0x12, 0x21);
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// ======= 初始化键盘循环队列缓冲区 ===========
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// 申请键盘循环队列缓冲区的内存
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