mirror of
https://github.com/DragonOS-Community/DragonOS.git
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7ae679ddd6
* bugfix: 修复了Flusher Drop的时候没有自动刷新TLB的bug * 解决进程管理未初始化时，trap.c尝试打印pid导致错误的问题 * 设置kmalloc默认强制清0 * 修复ahci驱动的内存越界问题 * 修复mmio buddy忘记归还buddy block的问题 * 新增acpi模块,暂时能解析acpi tables
409 lines
13 KiB
Rust
409 lines
13 KiB
Rust
use alloc::vec::Vec;
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use core::{intrinsics::size_of, ptr};
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use core::sync::atomic::compiler_fence;
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use crate::mm::phys_2_virt;
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/// 文件说明: 实现了 AHCI 中的控制器 HBA 的相关行为
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/// 根据 AHCI 写出 HBA 的 Command
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pub const ATA_CMD_READ_DMA_EXT: u8 = 0x25; // 读操作，并且退出
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pub const ATA_CMD_WRITE_DMA_EXT: u8 = 0x35; // 写操作，并且退出
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#[allow(dead_code)]
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pub const ATA_CMD_IDENTIFY: u8 = 0xEC;
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#[allow(dead_code)]
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pub const ATA_CMD_IDENTIFY_PACKET: u8 = 0xA1;
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#[allow(dead_code)]
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pub const ATA_CMD_PACKET: u8 = 0xA0;
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pub const ATA_DEV_BUSY: u8 = 0x80;
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pub const ATA_DEV_DRQ: u8 = 0x08;
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pub const HBA_PORT_CMD_CR: u32 = 1 << 15;
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pub const HBA_PORT_CMD_FR: u32 = 1 << 14;
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pub const HBA_PORT_CMD_FRE: u32 = 1 << 4;
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pub const HBA_PORT_CMD_ST: u32 = 1;
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#[allow(dead_code)]
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pub const HBA_PORT_IS_ERR: u32 = 1 << 30 | 1 << 29 | 1 << 28 | 1 << 27;
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pub const HBA_SSTS_PRESENT: u32 = 0x3;
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pub const HBA_SIG_ATA: u32 = 0x00000101;
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pub const HBA_SIG_ATAPI: u32 = 0xEB140101;
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pub const HBA_SIG_PM: u32 = 0x96690101;
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pub const HBA_SIG_SEMB: u32 = 0xC33C0101;
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/// 接入 Port 的 不同设备类型
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#[derive(Debug)]
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pub enum HbaPortType {
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None,
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Unknown(u32),
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SATA,
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SATAPI,
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PM,
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SEMB,
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}
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/// 声明了 HBA 的所有属性
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#[repr(packed)]
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pub struct HbaPort {
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pub clb: u64, // 0x00, command list base address, 1K-byte aligned
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pub fb: u64, // 0x08, FIS base address, 256-byte aligned
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pub is: u32, // 0x10, interrupt status
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pub ie: u32, // 0x14, interrupt enable
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pub cmd: u32, // 0x18, command and status
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pub _rsv0: u32, // 0x1C, Reserved
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pub tfd: u32, // 0x20, task file data
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pub sig: u32, // 0x24, signature
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pub ssts: u32, // 0x28, SATA status (SCR0:SStatus)
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pub sctl: u32, // 0x2C, SATA control (SCR2:SControl)
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pub serr: u32, // 0x30, SATA error (SCR1:SError)
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pub sact: u32, // 0x34, SATA active (SCR3:SActive)
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pub ci: u32, // 0x38, command issue
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pub sntf: u32, // 0x3C, SATA notification (SCR4:SNotification)
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pub fbs: u32, // 0x40, FIS-based switch control
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pub _rsv1: [u32; 11], // 0x44 ~ 0x6F, Reserved
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pub vendor: [u32; 4], // 0x70 ~ 0x7F, vendor specific
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}
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/// 全称 HBA Memory Register，是HBA的寄存器在内存中的映射
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#[repr(packed)]
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pub struct HbaMem {
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pub cap: u32, // 0x00, Host capability
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pub ghc: u32, // 0x04, Global host control
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pub is: u32, // 0x08, Interrupt status
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pub pi: u32, // 0x0C, Port implemented
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pub vs: u32, // 0x10, Version
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pub ccc_ctl: u32, // 0x14, Command completion coalescing control
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pub ccc_pts: u32, // 0x18, Command completion coalescing ports
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pub em_loc: u32, // 0x1C, Enclosure management location
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pub em_ctl: u32, // 0x20, Enclosure management control
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pub cap2: u32, // 0x24, Host capabilities extended
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pub bohc: u32, // 0x28, BIOS/OS handoff control and status
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pub _rsv: [u8; 116], // 0x2C - 0x9F, Reserved
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pub vendor: [u8; 96], // 0xA0 - 0xFF, Vendor specific registers
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pub ports: [HbaPort; 32], // 0x100 - 0x10FF, Port control registers
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}
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/// HBA Command Table 里面的 PRDT 项
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/// 作用: 记录了内存中读/写数据的位置，以及长度。你可以把他类比成一个指针？
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#[repr(packed)]
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pub struct HbaPrdtEntry {
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pub dba: u64, // Data base address
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_rsv0: u32, // Reserved
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pub dbc: u32, // Byte count, 4M max, interrupt = 1
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}
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/// HAB Command Table
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/// 每个 Port 一个 Table，主机和设备的交互都靠这个数据结构
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#[repr(packed)]
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pub struct HbaCmdTable {
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// 0x00
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pub cfis: [u8; 64], // Command FIS
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// 0x40
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pub acmd: [u8; 16], // ATAPI command, 12 or 16 bytes
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// 0x50
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_rsv: [u8; 48], // Reserved
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// 0x80
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pub prdt_entry: [HbaPrdtEntry; 8], // Physical region descriptor table entries, 0 ~ 65535, 需要注意不要越界 这里设置8的原因是，目前CmdTable只预留了8个PRDT项的空间
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}
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/// HBA Command Header
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/// 作用: 你可以把他类比成 Command Table 的指针。
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/// 猜测: 这里多了一层 Header，而不是直接在 HbaMem 结构体指向 CmdTable，可能是为了兼容和可移植性？
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#[repr(packed)]
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pub struct HbaCmdHeader {
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// DW0
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pub cfl: u8,
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// Command FIS length in DWORDS: 5(len in [2, 16]), atapi: 1, write - host to device: 1, prefetchable: 1
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pub _pm: u8, // Reset - 0x80, bist: 0x40, clear busy on ok: 0x20, port multiplier
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pub prdtl: u16, // Physical region descriptor table length in entries
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// DW1
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pub _prdbc: u32, // Physical region descriptor byte count transferred
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// DW2, 3
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pub ctba: u64, // Command table descriptor base address
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// DW4 - 7
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pub _rsv1: [u32; 4], // Reserved
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}
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/// Port 的函数实现
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impl HbaPort {
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/// 获取设备类型
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pub fn check_type(&mut self) -> HbaPortType {
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if volatile_read!(self.ssts) & HBA_SSTS_PRESENT > 0 {
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let sig = volatile_read!(self.sig);
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match sig {
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HBA_SIG_ATA => HbaPortType::SATA,
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HBA_SIG_ATAPI => HbaPortType::SATAPI,
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HBA_SIG_PM => HbaPortType::PM,
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HBA_SIG_SEMB => HbaPortType::SEMB,
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_ => HbaPortType::Unknown(sig),
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}
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} else {
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HbaPortType::None
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}
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}
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/// 启动该端口的命令引擎
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pub fn start(&mut self) {
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while volatile_read!(self.cmd) & HBA_PORT_CMD_CR > 0 {
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core::hint::spin_loop();
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}
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let val: u32 = volatile_read!(self.cmd) | HBA_PORT_CMD_FRE | HBA_PORT_CMD_ST;
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volatile_write!(self.cmd, val);
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}
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/// 关闭该端口的命令引擎
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pub fn stop(&mut self) {
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#[allow(unused_unsafe)]
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{
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volatile_write!(
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self.cmd,
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(u32::MAX ^ HBA_PORT_CMD_ST) & volatile_read!(self.cmd)
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);
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}
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while volatile_read!(self.cmd) & (HBA_PORT_CMD_FR | HBA_PORT_CMD_CR)
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== (HBA_PORT_CMD_FR | HBA_PORT_CMD_CR)
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{
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core::hint::spin_loop();
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}
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#[allow(unused_unsafe)]
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{
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volatile_write!(
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self.cmd,
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(u32::MAX ^ HBA_PORT_CMD_FRE) & volatile_read!(self.cmd)
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);
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}
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}
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/// @return: 返回一个空闲 cmd table 的 id; 如果没有，则返回 Option::None
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pub fn find_cmdslot(&self) -> Option<u32> {
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let slots = volatile_read!(self.sact) | volatile_read!(self.ci);
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for i in 0..32 {
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if slots & 1 << i == 0 {
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return Some(i);
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}
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}
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return None;
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}
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/// 初始化, 把 CmdList 等变量的地址赋值到 HbaPort 上 - 这些空间由操作系统分配且固定
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/// 等价于原C版本的 port_rebase 函数
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pub fn init(&mut self, clb: u64, fb: u64, ctbas: &Vec<u64>) {
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self.stop(); // 先暂停端口
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// 赋值 command list base address
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// Command list offset: 1K*portno
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// Command list entry size = 32
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// Command list entry maxim count = 32
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// Command list maxim size = 32*32 = 1K per port
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volatile_write!(self.clb, clb);
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unsafe {
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compiler_fence(core::sync::atomic::Ordering::SeqCst);
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ptr::write_bytes(phys_2_virt(clb as usize) as *mut u64, 0, 1024);
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}
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// 赋值 fis base address
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// FIS offset: 32K+256*portno
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// FIS entry size = 256 bytes per port
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volatile_write!(self.fb, fb);
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unsafe {
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compiler_fence(core::sync::atomic::Ordering::SeqCst);
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ptr::write_bytes(phys_2_virt(fb as usize) as *mut u64, 0, 256);
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}
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// 赋值 command table base address
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// Command table offset: 40K + 8K*portno
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// Command table size = 256*32 = 8K per port
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let mut cmdheaders = phys_2_virt(clb as usize) as *mut u64 as *mut HbaCmdHeader;
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for i in 0..32 as usize {
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volatile_write!((*cmdheaders).prdtl, 0); // 一开始没有询问，prdtl = 0（预留了8个PRDT项的空间）
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volatile_write!((*cmdheaders).ctba, ctbas[i]);
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// 这里限制了 prdtl <= 8, 所以一共用了256bytes，如果需要修改，可以修改这里
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compiler_fence(core::sync::atomic::Ordering::SeqCst);
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unsafe {
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ptr::write_bytes(phys_2_virt(ctbas[i] as usize) as *mut u64, 0, 256);
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}
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cmdheaders = (cmdheaders as usize + size_of::<HbaCmdHeader>()) as *mut HbaCmdHeader;
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}
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#[allow(unused_unsafe)]
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{
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// 启动中断
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volatile_write!(self.ie, 0 /*TODO: Enable interrupts: 0b10111*/);
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// 错误码
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volatile_write!(self.serr, volatile_read!(self.serr));
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// Disable power management
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volatile_write!(self.sctl, volatile_read!(self.sctl) | 7 << 8);
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// Power on and spin up device
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volatile_write!(self.cmd, volatile_read!(self.cmd) | 1 << 2 | 1 << 1);
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}
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self.start(); // 重新开启端口
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}
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}
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#[repr(u8)]
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#[allow(dead_code)]
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pub enum FisType {
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/// Register FIS - host to device
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RegH2D = 0x27,
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/// Register FIS - device to host
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RegD2H = 0x34,
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/// DMA activate FIS - device to host
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DmaAct = 0x39,
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/// DMA setup FIS - bidirectional
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DmaSetup = 0x41,
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/// Data FIS - bidirectional
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Data = 0x46,
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/// BIST activate FIS - bidirectional
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Bist = 0x58,
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/// PIO setup FIS - device to host
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PioSetup = 0x5F,
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/// Set device bits FIS - device to host
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DevBits = 0xA1,
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}
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#[repr(packed)]
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pub struct FisRegH2D {
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// DWORD 0
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pub fis_type: u8, // FIS_TYPE_REG_H2D
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pub pm: u8, // Port multiplier, 1: Command, 0: Control
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// uint8_t pmport : 4; // Port multiplier 低4位
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// uint8_t rsv0 : 3; // Reserved
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// uint8_t c : 1; // 1: Command, 0: Control
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pub command: u8, // Command register
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pub featurel: u8, // Feature register, 7:0
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// DWORD 1
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pub lba0: u8, // LBA low register, 7:0
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pub lba1: u8, // LBA mid register, 15:8
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pub lba2: u8, // LBA high register, 23:16
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pub device: u8, // Device register
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// DWORD 2
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pub lba3: u8, // LBA register, 31:24
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pub lba4: u8, // LBA register, 39:32
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pub lba5: u8, // LBA register, 47:40
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pub featureh: u8, // Feature register, 15:8
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// DWORD 3
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pub countl: u8, // Count register, 7:0
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pub counth: u8, // Count register, 15:8
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pub icc: u8, // Isochronous command completion
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pub control: u8, // Control register
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// DWORD 4
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pub rsv1: [u8; 4], // Reserved
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}
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#[repr(packed)]
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#[allow(dead_code)]
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pub struct FisRegD2H {
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// DWORD 0
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pub fis_type: u8, // FIS_TYPE_REG_D2H
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pub pm: u8, // Port multiplier, Interrupt bit: 2
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pub status: u8, // Status register
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pub error: u8, // Error register
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// DWORD 1
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pub lba0: u8, // LBA low register, 7:0
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pub lba1: u8, // LBA mid register, 15:8
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pub lba2: u8, // LBA high register, 23:16
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pub device: u8, // Device register
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// DWORD 2
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pub lba3: u8, // LBA register, 31:24
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pub lba4: u8, // LBA register, 39:32
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pub lba5: u8, // LBA register, 47:40
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pub rsv2: u8, // Reserved
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// DWORD 3
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pub countl: u8, // Count register, 7:0
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pub counth: u8, // Count register, 15:8
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pub rsv3: [u8; 2], // Reserved
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// DWORD 4
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pub rsv4: [u8; 4], // Reserved
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}
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#[repr(packed)]
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#[allow(dead_code)]
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pub struct FisData {
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// DWORD 0
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pub fis_type: u8, // FIS_TYPE_DATA
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pub pm: u8, // Port multiplier
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pub rsv1: [u8; 2], // Reserved
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// DWORD 1 ~ N
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pub data: [u8; 252], // Payload
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}
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#[repr(packed)]
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#[allow(dead_code)]
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pub struct FisPioSetup {
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// DWORD 0
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pub fis_type: u8, // FIS_TYPE_PIO_SETUP
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pub pm: u8, // Port multiplier, direction: 4 - device to host, interrupt: 2
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pub status: u8, // Status register
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pub error: u8, // Error register
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// DWORD 1
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pub lba0: u8, // LBA low register, 7:0
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pub lba1: u8, // LBA mid register, 15:8
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pub lba2: u8, // LBA high register, 23:16
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pub device: u8, // Device register
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// DWORD 2
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pub lba3: u8, // LBA register, 31:24
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pub lba4: u8, // LBA register, 39:32
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pub lba5: u8, // LBA register, 47:40
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pub rsv2: u8, // Reserved
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// DWORD 3
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pub countl: u8, // Count register, 7:0
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pub counth: u8, // Count register, 15:8
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pub rsv3: u8, // Reserved
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pub e_status: u8, // New value of status register
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// DWORD 4
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pub tc: u16, // Transfer count
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pub rsv4: [u8; 2], // Reserved
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}
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#[repr(packed)]
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#[allow(dead_code)]
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pub struct FisDmaSetup {
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// DWORD 0
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pub fis_type: u8, // FIS_TYPE_DMA_SETUP
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pub pm: u8, // Port multiplier, direction: 4 - device to host, interrupt: 2, auto-activate: 1
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pub rsv1: [u8; 2], // Reserved
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// DWORD 1&2
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pub dma_buffer_id: u64, /* DMA Buffer Identifier. Used to Identify DMA buffer in host memory. SATA Spec says host specific and not in Spec. Trying AHCI spec might work. */
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// DWORD 3
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pub rsv3: u32, // More reserved
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// DWORD 4
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pub dma_buffer_offset: u32, // Byte offset into buffer. First 2 bits must be 0
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// DWORD 5
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pub transfer_count: u32, // Number of bytes to transfer. Bit 0 must be 0
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// DWORD 6
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pub rsv6: u32, // Reserved
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}
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