mirror of
https://github.com/DragonOS-Community/DragonOS.git
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818 lines
29 KiB
Rust
818 lines
29 KiB
Rust
// 参考手册: PCIe* GbE Controllers Open Source Software Developer’s Manual
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// Refernce: PCIe* GbE Controllers Open Source Software Developer’s Manual
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use alloc::string::ToString;
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use alloc::sync::Arc;
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use alloc::vec::Vec;
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use core::intrinsics::unlikely;
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use core::mem::size_of;
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use core::ptr::NonNull;
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use core::slice::{from_raw_parts, from_raw_parts_mut};
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use core::sync::atomic::{compiler_fence, Ordering};
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use log::{debug, info};
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use super::e1000e_driver::e1000e_driver_init;
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use crate::driver::base::device::DeviceId;
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use crate::driver::net::dma::{dma_alloc, dma_dealloc};
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use crate::driver::net::irq_handle::DefaultNetIrqHandler;
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use crate::driver::pci::pci::{
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get_pci_device_structure_mut, PciDeviceStructure, PciDeviceStructureGeneralDevice, PciError,
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PCI_DEVICE_LINKEDLIST,
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};
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use crate::driver::pci::pci_irq::{IrqCommonMsg, IrqSpecificMsg, PciInterrupt, PciIrqMsg, IRQ};
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use crate::exception::IrqNumber;
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use crate::libs::volatile::{ReadOnly, Volatile, WriteOnly};
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const PAGE_SIZE: usize = 4096;
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const NETWORK_CLASS: u8 = 0x2;
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const ETHERNET_SUBCLASS: u8 = 0x0;
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// e1000e系列网卡的device id列表，来源：https://admin.pci-ids.ucw.cz/read/PC/8086
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const E1000E_DEVICE_ID: [u16; 14] = [
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0x10d3, // 8574L, qemu default
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0x10cc, // 82567LM-2
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0x10cd, // 82567LF-2
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0x105f, // 82571EB
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0x1060, // 82571EB
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0x107f, // 82572EI
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0x109a, // 82573L
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0x10ea, // 82577LM
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0x10eb, // 82577LC
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0x10ef, // 82578DM
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0x10f0, // 82578DC
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0x1502, // 82579LM
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0x1503, // 82579V
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0x150c, // 82583V
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];
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// e1000e网卡与BAR有关的常量
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// BAR0空间大小(128KB)
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const E1000E_BAR_REG_SIZE: u32 = 128 * 1024;
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// BAR0空间对齐(64bit)
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#[allow(dead_code)]
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const E1000E_BAR_REG_ALIGN: u8 = 64;
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// 单个寄存器大小(32bit, 4字节)
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#[allow(dead_code)]
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const E1000E_REG_SIZE: u8 = 4;
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// TxBuffer和RxBuffer的大小(DMA页)
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const E1000E_DMA_PAGES: usize = 1;
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// 中断相关
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const E1000E_RECV_VECTOR: IrqNumber = IrqNumber::new(57);
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// napi队列中暂时存储的buffer个数
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const E1000E_RECV_NAPI: usize = 1024;
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// 收/发包的描述符结构 pp.24 Table 3-1
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#[repr(C)]
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#[derive(Copy, Clone, Debug)]
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struct E1000ETransDesc {
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addr: u64,
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len: u16,
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cso: u8,
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cmd: u8,
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status: u8,
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css: u8,
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special: u8,
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}
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// pp.54 Table 3-12
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#[repr(C)]
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#[derive(Copy, Clone, Debug)]
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struct E1000ERecvDesc {
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addr: u64,
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len: u16,
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chksum: u16,
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status: u16,
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error: u8,
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special: u8,
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}
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#[derive(Copy, Clone)]
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// Buffer的Copy只是指针操作，不涉及实际数据的复制，因此要小心使用，确保不同的buffer不会使用同一块内存
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pub struct E1000EBuffer {
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buffer: NonNull<u8>,
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paddr: usize,
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// length字段为0则表示这个buffer是一个占位符，不指向实际内存
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// the buffer is empty and no page is allocated if length field is set 0
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length: usize,
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}
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impl E1000EBuffer {
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pub fn new(length: usize) -> Self {
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assert!(length <= PAGE_SIZE);
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if unlikely(length == 0) {
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// 在某些情况下，我们并不需要实际分配buffer，只需要提供一个占位符即可
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// we dont need to allocate dma pages for buffer in some cases
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E1000EBuffer {
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buffer: NonNull::dangling(),
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paddr: 0,
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length: 0,
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}
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} else {
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let (paddr, vaddr) = dma_alloc(E1000E_DMA_PAGES);
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E1000EBuffer {
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buffer: vaddr,
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paddr,
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length,
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}
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}
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}
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#[allow(dead_code)]
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pub fn as_addr(&self) -> NonNull<u8> {
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assert!(self.length != 0);
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return self.buffer;
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}
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#[allow(dead_code)]
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pub fn as_addr_u64(&self) -> u64 {
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assert!(self.length != 0);
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return self.buffer.as_ptr() as u64;
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}
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pub fn as_paddr(&self) -> usize {
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assert!(self.length != 0);
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return self.paddr;
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}
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#[allow(dead_code)]
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pub fn as_slice(&self) -> &[u8] {
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assert!(self.length != 0);
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return unsafe { from_raw_parts(self.buffer.as_ptr(), self.length) };
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}
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pub fn as_mut_slice(&mut self) -> &mut [u8] {
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assert!(self.length != 0);
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return unsafe { from_raw_parts_mut(self.buffer.as_ptr(), self.length) };
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}
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pub fn set_length(&mut self, length: usize) {
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self.length = length;
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}
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pub fn len(&self) -> usize {
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return self.length;
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}
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// 释放buffer内部的dma_pages，需要小心使用
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pub fn free_buffer(self) {
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if self.length != 0 {
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unsafe { dma_dealloc(self.paddr, self.buffer, E1000E_DMA_PAGES) };
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}
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}
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}
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#[allow(dead_code)]
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pub struct E1000EDevice {
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// 设备寄存器
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// device registers
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general_regs: NonNull<GeneralRegs>,
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interrupt_regs: NonNull<InterruptRegs>,
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rctl_regs: NonNull<ReceiveCtrlRegs>,
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receive_regs: NonNull<ReceiveRegs>,
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tctl_regs: NonNull<TransmitCtrlRegs>,
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transimit_regs: NonNull<TransimitRegs>,
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pcie_regs: NonNull<PCIeRegs>,
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// descriptor环形队列，在操作系统与设备之间共享
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// descriptor rings are shared between os and device
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recv_desc_ring: &'static mut [E1000ERecvDesc],
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trans_desc_ring: &'static mut [E1000ETransDesc],
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recv_ring_pa: usize,
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trans_ring_pa: usize,
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// 设备收/发包缓冲区数组
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// buffers of receive/transmit packets
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recv_buffers: Vec<E1000EBuffer>,
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trans_buffers: Vec<E1000EBuffer>,
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mac: [u8; 6],
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first_trans: bool,
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// napi队列，用于存放在中断关闭期间通过轮询收取的buffer
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// the napi queue is designed to save buffer/packet when the interrupt is close
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// NOTE: this feature is not completely implemented and not used in the current version
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napi_buffers: Vec<E1000EBuffer>,
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napi_buffer_head: usize,
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napi_buffer_tail: usize,
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napi_buffer_empty: bool,
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}
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impl E1000EDevice {
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// 从PCI标准设备进行驱动初始化
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// init the device for PCI standard device struct
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#[allow(unused_assignments)]
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pub fn new(
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device: &mut PciDeviceStructureGeneralDevice,
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device_id: Arc<DeviceId>,
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) -> Result<Self, E1000EPciError> {
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// 从BAR0获取我们需要的寄存器
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// Build registers sturcts from BAR0
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device.bar_ioremap().unwrap()?;
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device.enable_master();
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let bar = device.bar().ok_or(E1000EPciError::BarGetFailed)?;
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let bar0 = bar.get_bar(0)?;
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let (address, size) = bar0
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.memory_address_size()
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.ok_or(E1000EPciError::UnexpectedBarType)?;
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if address == 0 {
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return Err(E1000EPciError::BarNotAllocated);
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}
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if size != E1000E_BAR_REG_SIZE {
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return Err(E1000EPciError::UnexpectedBarSize);
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}
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let vaddress = bar0
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.virtual_address()
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.ok_or(E1000EPciError::BarGetVaddrFailed)?
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.data() as u64;
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// 初始化msi中断
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// initialize msi interupt
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let irq_vector = device.irq_vector_mut().unwrap();
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irq_vector.push(E1000E_RECV_VECTOR);
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device.irq_init(IRQ::PCI_IRQ_MSI).expect("IRQ Init Failed");
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let msg = PciIrqMsg {
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irq_common_message: IrqCommonMsg::init_from(
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0,
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"E1000E_RECV_IRQ".to_string(),
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&DefaultNetIrqHandler,
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device_id,
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),
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irq_specific_message: IrqSpecificMsg::msi_default(),
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};
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device.irq_install(msg)?;
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device.irq_enable(true)?;
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let general_regs: NonNull<GeneralRegs> =
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get_register_ptr(vaddress, E1000E_GENERAL_REGS_OFFSET);
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let interrupt_regs: NonNull<InterruptRegs> =
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get_register_ptr(vaddress, E1000E_INTERRRUPT_REGS_OFFSET);
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let rctl_regs: NonNull<ReceiveCtrlRegs> =
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get_register_ptr(vaddress, E1000E_RECEIVE_CTRL_REG_OFFSET);
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let receive_regs: NonNull<ReceiveRegs> =
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get_register_ptr(vaddress, E1000E_RECEIVE_REGS_OFFSET);
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let tctl_regs: NonNull<TransmitCtrlRegs> =
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get_register_ptr(vaddress, E1000E_TRANSMIT_CTRL_REG_OFFSET);
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let transimit_regs: NonNull<TransimitRegs> =
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get_register_ptr(vaddress, E1000E_TRANSMIT_REGS_OFFSET);
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let pcie_regs: NonNull<PCIeRegs> = get_register_ptr(vaddress, E1000E_PCIE_REGS_OFFSET);
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let ra_regs: NonNull<ReceiveAddressRegs> =
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get_register_ptr(vaddress, E1000E_RECEIVE_ADDRESS_REGS_OFFSET);
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// 开始设备初始化 14.3
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// Initialization Sequence
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unsafe {
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let mut ctrl = volread!(general_regs, ctrl);
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// 关闭中断
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// close the interrupt
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volwrite!(interrupt_regs, imc, E1000E_IMC_CLEAR);
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//SW RESET
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volwrite!(general_regs, ctrl, ctrl | E1000E_CTRL_RST);
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compiler_fence(Ordering::AcqRel);
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// PHY RESET
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ctrl = volread!(general_regs, ctrl);
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volwrite!(general_regs, ctrl, ctrl | E1000E_CTRL_PHY_RST);
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volwrite!(general_regs, ctrl, ctrl);
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// 关闭中断
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// close the interrupt
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volwrite!(interrupt_regs, imc, E1000E_IMC_CLEAR);
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let mut gcr = volread!(pcie_regs, gcr);
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gcr |= 1 << 22;
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volwrite!(pcie_regs, gcr, gcr);
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compiler_fence(Ordering::AcqRel);
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// PHY Initialization 14.8.1
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// MAC/PHY Link Setup 14.8.2
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ctrl = volread!(general_regs, ctrl);
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ctrl &= !(E1000E_CTRL_FRCSPD | E1000E_CTRL_FRCDPLX);
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volwrite!(general_regs, ctrl, ctrl | E1000E_CTRL_SLU);
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}
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let status = unsafe { volread!(general_regs, status) };
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debug!("Status: {status:#X}");
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// 读取设备的mac地址
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// Read mac address
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let ral = unsafe { volread!(ra_regs, ral0) };
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let rah = unsafe { volread!(ra_regs, rah0) };
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let mac: [u8; 6] = [
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(ral & 0xFF) as u8,
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((ral >> 8) & 0xFF) as u8,
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((ral >> 16) & 0xFF) as u8,
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((ral >> 24) & 0xFF) as u8,
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(rah & 0xFF) as u8,
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((rah >> 8) & 0xFF) as u8,
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];
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// 初始化receive和transimit descriptor环形队列
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// initialize receive and transimit desciptor ring
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let (recv_ring_pa, recv_ring_va) = dma_alloc(E1000E_DMA_PAGES);
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let (trans_ring_pa, trans_ring_va) = dma_alloc(E1000E_DMA_PAGES);
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let recv_ring_length = PAGE_SIZE / size_of::<E1000ERecvDesc>();
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let trans_ring_length = PAGE_SIZE / size_of::<E1000ETransDesc>();
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let recv_desc_ring = unsafe {
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from_raw_parts_mut::<E1000ERecvDesc>(recv_ring_va.as_ptr().cast(), recv_ring_length)
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};
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let trans_desc_ring = unsafe {
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from_raw_parts_mut::<E1000ETransDesc>(trans_ring_va.as_ptr().cast(), trans_ring_length)
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};
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// 初始化receive和transmit packet的缓冲区
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// initialzie receive and transmit buffers
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let mut recv_buffers: Vec<E1000EBuffer> = Vec::with_capacity(recv_ring_length);
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let mut trans_buffers: Vec<E1000EBuffer> = Vec::with_capacity(trans_ring_length);
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// 初始化缓冲区与descriptor，descriptor 中的addr字典应当指向buffer的物理地址
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// Receive buffers of appropriate size should be allocated and pointers to these buffers should be stored in the descriptor ring.
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for ring in recv_desc_ring.iter_mut().take(recv_ring_length) {
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let buffer = E1000EBuffer::new(PAGE_SIZE);
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ring.addr = buffer.as_paddr() as u64;
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ring.status = 0;
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recv_buffers.push(buffer);
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}
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// Same as receive buffers
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for ring in trans_desc_ring.iter_mut().take(recv_ring_length) {
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let buffer = E1000EBuffer::new(PAGE_SIZE);
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ring.addr = buffer.as_paddr() as u64;
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ring.status = 1;
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trans_buffers.push(buffer);
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}
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// Receive Initialization 14.6
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// Initialzie mutlicast table array to 0b
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// 初始化MTA，遍历0x05200-0x053FC中每个寄存器，写入0b，一共128个寄存器
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let mut mta_adress = vaddress + E1000E_MTA_REGS_START_OFFSET;
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while mta_adress != vaddress + E1000E_MTA_REGS_END_OFFSET {
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let mta: NonNull<MTARegs> = get_register_ptr(mta_adress, 0);
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unsafe { volwrite!(mta, mta, 0) };
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mta_adress += 4;
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}
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// 连续的寄存器读-写操作，放在同一个unsafe块中
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unsafe {
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// 设置descriptor环形队列的基地址
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// Program the descriptor base address with the address of the region.
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volwrite!(receive_regs, rdbal0, (recv_ring_pa) as u32);
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volwrite!(receive_regs, rdbah0, (recv_ring_pa >> 32) as u32);
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// 设置descriptor环形队列的长度
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// Set the length register to the size of the descriptor ring.
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volwrite!(receive_regs, rdlen0, PAGE_SIZE as u32);
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// 设置队列的首尾指针
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// Program the head and tail registers
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volwrite!(receive_regs, rdh0, 0);
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volwrite!(receive_regs, rdt0, (recv_ring_length - 1) as u32);
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// 设置控制寄存器的相关功能 14.6.1
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// Set the receive control register
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volwrite!(
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rctl_regs,
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rctl,
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E1000E_RCTL_EN
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| E1000E_RCTL_BAM
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| E1000E_RCTL_BSIZE_4K
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| E1000E_RCTL_BSEX
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| E1000E_RCTL_SECRC
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);
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// Transmit Initialization 14.7
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// 开启发包descriptor的回写功能
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// Program the TXDCTL register with the desired TX descriptor write-back policy
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volwrite!(
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transimit_regs,
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txdctl,
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E1000E_TXDCTL_WTHRESH | E1000E_TXDCTL_GRAN
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);
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// 设置descriptor环形队列的基地址，长度与首尾指针
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// Program the descriptor base address with the address of the region
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volwrite!(transimit_regs, tdbal0, trans_ring_pa as u32);
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volwrite!(transimit_regs, tdbah0, (trans_ring_pa >> 32) as u32);
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// Set the length register to the size of the descriptor ring.
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volwrite!(transimit_regs, tdlen0, PAGE_SIZE as u32);
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// Program the head and tail registerss
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volwrite!(transimit_regs, tdh0, 0);
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volwrite!(transimit_regs, tdt0, 0);
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// Program the TIPG register
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volwrite!(
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tctl_regs,
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tipg,
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E1000E_TIPG_IPGT | E1000E_TIPG_IPGR1 | E1000E_TIPG_IPGR2
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);
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// Program the TCTL register.
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volwrite!(
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tctl_regs,
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tctl,
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E1000E_TCTL_EN | E1000E_TCTL_PSP | E1000E_TCTL_CT_VAL | E1000E_TCTL_COLD_VAL
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);
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let icr = volread!(interrupt_regs, icr);
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volwrite!(interrupt_regs, icr, icr);
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// 开启收包相关的中断
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// Enable receive interrupts
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let mut ims = volread!(interrupt_regs, ims);
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ims = E1000E_IMS_LSC | E1000E_IMS_RXT0 | E1000E_IMS_RXDMT0 | E1000E_IMS_OTHER;
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volwrite!(interrupt_regs, ims, ims);
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}
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return Ok(E1000EDevice {
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general_regs,
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interrupt_regs,
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rctl_regs,
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receive_regs,
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tctl_regs,
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transimit_regs,
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pcie_regs,
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recv_desc_ring,
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trans_desc_ring,
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recv_ring_pa,
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trans_ring_pa,
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recv_buffers,
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trans_buffers,
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mac,
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first_trans: true,
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napi_buffers: vec![E1000EBuffer::new(0); E1000E_RECV_NAPI],
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napi_buffer_head: 0,
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napi_buffer_tail: 0,
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napi_buffer_empty: true,
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});
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}
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pub fn e1000e_receive(&mut self) -> Option<E1000EBuffer> {
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self.e1000e_intr();
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let mut rdt = unsafe { volread!(self.receive_regs, rdt0) } as usize;
|
||
let index = (rdt + 1) % self.recv_desc_ring.len();
|
||
let desc = &mut self.recv_desc_ring[index];
|
||
if (desc.status & E1000E_RXD_STATUS_DD) == 0 {
|
||
return None;
|
||
}
|
||
let mut buffer = self.recv_buffers[index];
|
||
let new_buffer = E1000EBuffer::new(PAGE_SIZE);
|
||
self.recv_buffers[index] = new_buffer;
|
||
desc.addr = new_buffer.as_paddr() as u64;
|
||
buffer.set_length(desc.len as usize);
|
||
rdt = index;
|
||
unsafe { volwrite!(self.receive_regs, rdt0, rdt as u32) };
|
||
// debug!("e1000e: receive packet");
|
||
return Some(buffer);
|
||
}
|
||
|
||
pub fn e1000e_can_transmit(&self) -> bool {
|
||
let tdt = unsafe { volread!(self.transimit_regs, tdt0) } as usize;
|
||
let index = tdt % self.trans_desc_ring.len();
|
||
let desc = &self.trans_desc_ring[index];
|
||
if (desc.status & E1000E_TXD_STATUS_DD) == 0 {
|
||
return false;
|
||
}
|
||
true
|
||
}
|
||
|
||
pub fn e1000e_transmit(&mut self, packet: E1000EBuffer) {
|
||
let mut tdt = unsafe { volread!(self.transimit_regs, tdt0) } as usize;
|
||
let index = tdt % self.trans_desc_ring.len();
|
||
let desc = &mut self.trans_desc_ring[index];
|
||
let buffer = self.trans_buffers[index];
|
||
self.trans_buffers[index] = packet;
|
||
// recycle unused transmit buffer
|
||
buffer.free_buffer();
|
||
// Set the transmit descriptor
|
||
desc.addr = packet.as_paddr() as u64;
|
||
desc.len = packet.len() as u16;
|
||
desc.status = 0;
|
||
desc.cmd = E1000E_TXD_CMD_EOP | E1000E_TXD_CMD_RS | E1000E_TXD_CMD_IFCS;
|
||
tdt = (tdt + 1) % self.trans_desc_ring.len();
|
||
unsafe { volwrite!(self.transimit_regs, tdt0, tdt as u32) };
|
||
self.first_trans = false;
|
||
}
|
||
pub fn mac_address(&self) -> [u8; 6] {
|
||
return self.mac;
|
||
}
|
||
// 向ICR寄存器中的某一bit写入1b表示该中断已经被接收，同时会清空该位
|
||
// we need to clear ICR to tell e1000e we have read the interrupt
|
||
pub fn e1000e_intr(&mut self) {
|
||
let icr = unsafe { volread!(self.interrupt_regs, icr) };
|
||
// write 1b to any bit in ICR will clear the bit
|
||
unsafe { volwrite!(self.interrupt_regs, icr, icr) };
|
||
}
|
||
|
||
// 切换是否接受分组到达的中断
|
||
// change whether the receive timer interrupt is enabled
|
||
// Note: this method is not completely implemented and not used in the current version
|
||
#[allow(dead_code)]
|
||
pub fn e1000e_intr_set(&mut self, state: bool) {
|
||
let mut ims = unsafe { volread!(self.interrupt_regs, ims) };
|
||
match state {
|
||
true => ims |= E1000E_IMS_RXT0,
|
||
false => ims &= !E1000E_IMS_RXT0,
|
||
}
|
||
unsafe { volwrite!(self.interrupt_regs, ims, ims) };
|
||
}
|
||
|
||
// 实现了一部分napi机制的收包函数, 现在还没有投入使用
|
||
// This method is a partial implementation of napi (New API) techniques
|
||
// Note: this method is not completely implemented and not used in the current version
|
||
#[allow(dead_code)]
|
||
pub fn e1000e_receive2(&mut self) -> Option<E1000EBuffer> {
|
||
// 向设备表明我们已经接受到了之前的中断
|
||
// Tell e1000e we have received the interrupt
|
||
self.e1000e_intr();
|
||
// 如果napi队列不存在已经收到的分组...
|
||
// if napi queue is empty...
|
||
if self.napi_buffer_empty {
|
||
// 暂时关闭设备中断
|
||
// close interrupt
|
||
self.e1000e_intr_set(false);
|
||
loop {
|
||
if self.napi_buffer_tail == self.napi_buffer_head && !self.napi_buffer_empty {
|
||
// napi缓冲队列已满，停止收包
|
||
// napi queue is full, stop
|
||
break;
|
||
}
|
||
match self.e1000e_receive() {
|
||
Some(buffer) => {
|
||
self.napi_buffers[self.napi_buffer_tail] = buffer;
|
||
self.napi_buffer_tail = (self.napi_buffer_tail + 1) % E1000E_RECV_NAPI;
|
||
self.napi_buffer_empty = false;
|
||
}
|
||
None => {
|
||
// 设备队列中没有剩余的已到达的数据包
|
||
// no packet remains in the device buffer
|
||
break;
|
||
}
|
||
};
|
||
}
|
||
// 重新打开设备中断
|
||
// open the interrupt
|
||
self.e1000e_intr_set(true);
|
||
}
|
||
|
||
let result = self.napi_buffers[self.napi_buffer_head];
|
||
match result.len() {
|
||
0 => {
|
||
// napi队列和网卡队列中都不存在数据包
|
||
// both napi queue and device buffer is empty, no packet will receive
|
||
return None;
|
||
}
|
||
_ => {
|
||
// 有剩余的已到达的数据包
|
||
// there is packet in napi queue
|
||
self.napi_buffer_head = (self.napi_buffer_head + 1) % E1000E_RECV_NAPI;
|
||
if self.napi_buffer_head == self.napi_buffer_tail {
|
||
self.napi_buffer_empty = true;
|
||
}
|
||
return Some(result);
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
impl Drop for E1000EDevice {
|
||
fn drop(&mut self) {
|
||
// 释放已分配的所有dma页
|
||
// free all dma pages we have allocated
|
||
debug!("droping...");
|
||
let recv_ring_length = PAGE_SIZE / size_of::<E1000ERecvDesc>();
|
||
let trans_ring_length = PAGE_SIZE / size_of::<E1000ETransDesc>();
|
||
unsafe {
|
||
// 释放所有buffer中的dma页
|
||
// free all dma pages in buffers
|
||
for i in 0..recv_ring_length {
|
||
self.recv_buffers[i].free_buffer();
|
||
}
|
||
for i in 0..trans_ring_length {
|
||
self.trans_buffers[i].free_buffer();
|
||
}
|
||
// 释放descriptor ring
|
||
// free descriptor ring
|
||
dma_dealloc(
|
||
self.recv_ring_pa,
|
||
NonNull::new(self.recv_desc_ring).unwrap().cast(),
|
||
E1000E_DMA_PAGES,
|
||
);
|
||
dma_dealloc(
|
||
self.trans_ring_pa,
|
||
NonNull::new(self.trans_desc_ring).unwrap().cast(),
|
||
E1000E_DMA_PAGES,
|
||
);
|
||
}
|
||
}
|
||
}
|
||
|
||
pub fn e1000e_init() {
|
||
match e1000e_probe() {
|
||
Ok(_code) => {
|
||
info!("Successfully init e1000e device!");
|
||
}
|
||
Err(_error) => {
|
||
info!("Error occurred!");
|
||
}
|
||
}
|
||
}
|
||
|
||
pub fn e1000e_probe() -> Result<u64, E1000EPciError> {
|
||
let mut list = PCI_DEVICE_LINKEDLIST.write();
|
||
let result = get_pci_device_structure_mut(&mut list, NETWORK_CLASS, ETHERNET_SUBCLASS);
|
||
if result.is_empty() {
|
||
return Ok(0);
|
||
}
|
||
for device in result {
|
||
let standard_device = device.as_standard_device_mut().unwrap();
|
||
let header = &standard_device.common_header;
|
||
if header.vendor_id == 0x8086 {
|
||
// intel
|
||
if E1000E_DEVICE_ID.contains(&header.device_id) {
|
||
debug!(
|
||
"Detected e1000e PCI device with device id {:#x}",
|
||
header.device_id
|
||
);
|
||
|
||
// todo: 根据pci的path来生成device id
|
||
let e1000e = E1000EDevice::new(
|
||
standard_device,
|
||
DeviceId::new(None, Some(format!("e1000e_{}", header.device_id))).unwrap(),
|
||
)?;
|
||
e1000e_driver_init(e1000e);
|
||
}
|
||
}
|
||
}
|
||
|
||
return Ok(1);
|
||
}
|
||
|
||
// 用到的e1000e寄存器结构体
|
||
// pp.275, Table 13-3
|
||
// 设备通用寄存器
|
||
#[allow(dead_code)]
|
||
struct GeneralRegs {
|
||
ctrl: Volatile<u32>, //0x00000
|
||
ctrl_alias: Volatile<u32>, //0x00004
|
||
status: ReadOnly<u32>, //0x00008
|
||
status_align: ReadOnly<u32>, //0x0000c
|
||
eec: Volatile<u32>, //0x00010
|
||
eerd: Volatile<u32>, //0x00014
|
||
ctrl_ext: Volatile<u32>, //0x00018
|
||
fla: Volatile<u32>, //0x0001c
|
||
mdic: Volatile<u32>, //0x00020
|
||
}
|
||
// 中断控制
|
||
#[allow(dead_code)]
|
||
struct InterruptRegs {
|
||
icr: Volatile<u32>, //0x000c0 ICR寄存器应当为只读寄存器，但我们需要向其中写入来清除对应位
|
||
itr: Volatile<u32>, //0x000c4
|
||
ics: WriteOnly<u32>, //0x000c8
|
||
ics_align: ReadOnly<u32>, //0x000cc
|
||
ims: Volatile<u32>, //0x000d0
|
||
ims_align: ReadOnly<u32>, //0x000d4
|
||
imc: WriteOnly<u32>, //0x000d8
|
||
}
|
||
// 收包功能控制
|
||
struct ReceiveCtrlRegs {
|
||
rctl: Volatile<u32>, //0x00100
|
||
}
|
||
// 发包功能控制
|
||
#[allow(dead_code)]
|
||
struct TransmitCtrlRegs {
|
||
tctl: Volatile<u32>, //0x00400
|
||
tctl_ext: Volatile<u32>, //0x00404
|
||
unused_1: ReadOnly<u32>, //0x00408
|
||
unused_2: ReadOnly<u32>, //0x0040c
|
||
tipg: Volatile<u32>, //0x00410
|
||
}
|
||
// 收包功能相关
|
||
#[allow(dead_code)]
|
||
struct ReceiveRegs {
|
||
rdbal0: Volatile<u32>, //0x02800
|
||
rdbah0: Volatile<u32>, //0x02804
|
||
rdlen0: Volatile<u32>, //0x02808
|
||
rdl_align: ReadOnly<u32>, //0x0280c
|
||
rdh0: Volatile<u32>, //0x02810
|
||
rdh_align: ReadOnly<u32>, //0x02814
|
||
rdt0: Volatile<u32>, //0x02818
|
||
rdt_align: ReadOnly<u32>, //0x281c
|
||
rdtr: Volatile<u32>, //0x2820
|
||
rdtr_align: ReadOnly<u32>, //0x2824
|
||
rxdctl: Volatile<u32>, //0x2828
|
||
}
|
||
// 发包功能相关
|
||
#[allow(dead_code)]
|
||
struct TransimitRegs {
|
||
tdbal0: Volatile<u32>, //0x03800
|
||
tdbah0: Volatile<u32>, //0x03804
|
||
tdlen0: Volatile<u32>, //0x03808
|
||
tdlen_algin: ReadOnly<u32>, //0x0380c
|
||
tdh0: Volatile<u32>, //0x03810
|
||
tdh_align: ReadOnly<u32>, //0x03814
|
||
tdt0: Volatile<u32>, //0x03818
|
||
tdt_align: ReadOnly<u32>, //0x0381c
|
||
tidv: Volatile<u32>, //0x03820
|
||
tidv_align: ReadOnly<u32>, //0x03824
|
||
txdctl: Volatile<u32>, //0x03828
|
||
tadv: Volatile<u32>, //0x0382c
|
||
}
|
||
// mac地址
|
||
struct ReceiveAddressRegs {
|
||
ral0: Volatile<u32>, //0x05400
|
||
rah0: Volatile<u32>, //0x05404
|
||
}
|
||
// PCIe 通用控制
|
||
struct PCIeRegs {
|
||
gcr: Volatile<u32>, //0x05b00
|
||
}
|
||
#[allow(dead_code)]
|
||
struct StatisticsRegs {}
|
||
|
||
// 0x05200-0x053fc
|
||
// 在Receive Initialization 中按照每次一个32bit寄存器的方式来遍历
|
||
// Multicast Table Array Registers will be written per 32bit
|
||
struct MTARegs {
|
||
mta: Volatile<u32>,
|
||
}
|
||
|
||
const E1000E_GENERAL_REGS_OFFSET: u64 = 0x00000;
|
||
const E1000E_INTERRRUPT_REGS_OFFSET: u64 = 0x000c0;
|
||
const E1000E_RECEIVE_CTRL_REG_OFFSET: u64 = 0x00100;
|
||
const E1000E_RECEIVE_REGS_OFFSET: u64 = 0x02800;
|
||
const E1000E_TRANSMIT_CTRL_REG_OFFSET: u64 = 0x00400;
|
||
const E1000E_TRANSMIT_REGS_OFFSET: u64 = 0x03800;
|
||
const E1000E_RECEIVE_ADDRESS_REGS_OFFSET: u64 = 0x05400;
|
||
const E1000E_PCIE_REGS_OFFSET: u64 = 0x05b00;
|
||
const E1000E_MTA_REGS_START_OFFSET: u64 = 0x05200;
|
||
const E1000E_MTA_REGS_END_OFFSET: u64 = 0x053fc;
|
||
// 寄存器的特定位
|
||
//CTRL
|
||
const E1000E_CTRL_SLU: u32 = 1 << 6;
|
||
const E1000E_CTRL_FRCSPD: u32 = 1 << 11;
|
||
const E1000E_CTRL_FRCDPLX: u32 = 1 << 12;
|
||
const E1000E_CTRL_RST: u32 = 1 << 26;
|
||
#[allow(dead_code)]
|
||
const E1000E_CTRL_RFCE: u32 = 1 << 27;
|
||
#[allow(dead_code)]
|
||
const E1000E_CTRL_TFCE: u32 = 1 << 28;
|
||
const E1000E_CTRL_PHY_RST: u32 = 1 << 31;
|
||
|
||
// IMS
|
||
const E1000E_IMS_LSC: u32 = 1 << 2;
|
||
const E1000E_IMS_RXDMT0: u32 = 1 << 4;
|
||
#[allow(dead_code)]
|
||
const E1000E_IMS_RXO: u32 = 1 << 6;
|
||
const E1000E_IMS_RXT0: u32 = 1 << 7;
|
||
#[allow(dead_code)]
|
||
const E1000E_IMS_RXQ0: u32 = 1 << 20;
|
||
const E1000E_IMS_OTHER: u32 = 1 << 24; // qemu use this bit to set msi-x interrupt
|
||
|
||
// IMC
|
||
const E1000E_IMC_CLEAR: u32 = 0xffffffff;
|
||
|
||
// RCTL
|
||
const E1000E_RCTL_EN: u32 = 1 << 1;
|
||
const E1000E_RCTL_BAM: u32 = 1 << 15;
|
||
const E1000E_RCTL_BSIZE_4K: u32 = 3 << 16;
|
||
const E1000E_RCTL_BSEX: u32 = 1 << 25;
|
||
const E1000E_RCTL_SECRC: u32 = 1 << 26;
|
||
|
||
// TCTL
|
||
const E1000E_TCTL_EN: u32 = 1 << 1;
|
||
const E1000E_TCTL_PSP: u32 = 1 << 3;
|
||
const E1000E_TCTL_CT_VAL: u32 = 0x0f << 4; // suggested 16d collision, 手册建议值：16d
|
||
const E1000E_TCTL_COLD_VAL: u32 = 0x03f << 12; // suggested 64 byte time for Full-Duplex, 手册建议值：64
|
||
// TXDCTL
|
||
const E1000E_TXDCTL_WTHRESH: u32 = 1 << 16;
|
||
const E1000E_TXDCTL_GRAN: u32 = 1 << 24;
|
||
// TIPG
|
||
const E1000E_TIPG_IPGT: u32 = 8;
|
||
const E1000E_TIPG_IPGR1: u32 = 2 << 10;
|
||
const E1000E_TIPG_IPGR2: u32 = 10 << 20;
|
||
|
||
// RxDescriptorStatus
|
||
const E1000E_RXD_STATUS_DD: u16 = 1 << 0;
|
||
|
||
// TxDescriptorStatus
|
||
const E1000E_TXD_STATUS_DD: u8 = 1 << 0;
|
||
const E1000E_TXD_CMD_EOP: u8 = 1 << 0;
|
||
const E1000E_TXD_CMD_IFCS: u8 = 1 << 1;
|
||
const E1000E_TXD_CMD_RS: u8 = 1 << 3;
|
||
|
||
/// E1000E驱动初始化过程中可能的错误
|
||
#[allow(dead_code)]
|
||
pub enum E1000EPciError {
|
||
// 获取到错误类型的BAR（IO BAR）
|
||
// An IO BAR was provided rather than a memory BAR.
|
||
UnexpectedBarType,
|
||
// 获取的BAR没有被分配到某个地址(address == 0)
|
||
// A BAR which we need was not allocated an address(address == 0).
|
||
BarNotAllocated,
|
||
//获取虚拟地址失败
|
||
BarGetVaddrFailed,
|
||
// 没有对应的BAR或者获取BAR失败
|
||
BarGetFailed,
|
||
// BAR的大小与预期不符(128KB)
|
||
// Size of BAR is not 128KB
|
||
UnexpectedBarSize,
|
||
Pci(PciError),
|
||
}
|
||
|
||
/// PCI error到VirtioPciError的转换，层层上报
|
||
impl From<PciError> for E1000EPciError {
|
||
fn from(error: PciError) -> Self {
|
||
Self::Pci(error)
|
||
}
|
||
}
|
||
|
||
/**
|
||
* @brief 获取基地址的某个偏移量的指针，用于在mmio bar中构造寄存器结构体
|
||
* @brief used for build register struct in mmio bar
|
||
* @param vaddr: base address (in virtual memory)
|
||
* @param offset: offset
|
||
*/
|
||
fn get_register_ptr<T>(vaddr: u64, offset: u64) -> NonNull<T> {
|
||
NonNull::new((vaddr + offset) as *mut T).unwrap()
|
||
}
|