Adjust RISC-V's implementation for recent changes

kernel/src/arch/riscv/cpu.rs

@@ -1,7 +1,9 @@
 // SPDX-License-Identifier: MPL-2.0
 
+use alloc::{format, string::String};
+
 use ostd::{
-    cpu::{CpuExceptionInfo, RawGeneralRegs, UserContext},
+    cpu::context::{CpuExceptionInfo, RawGeneralRegs, UserContext},
     Pod,
 };
 
@@ -12,6 +14,10 @@ impl LinuxAbi for UserContext {
         self.a7()
     }
 
+    fn set_syscall_num(&mut self, num: usize) {
+        self.set_a7(num);
+    }
+
     fn syscall_ret(&self) -> usize {
         self.a0()
     }
@@ -146,3 +152,22 @@ impl TryFrom<&CpuExceptionInfo> for PageFaultInfo {
         })
     }
 }
+
+/// CPU Information structure.
+// TODO: Implement CPU information retrieval on RISC-V platforms.
+pub struct CpuInfo {
+    processor: u32,
+}
+
+impl CpuInfo {
+    pub fn new(processor_id: u32) -> Self {
+        Self {
+            processor: processor_id,
+        }
+    }
+
+    /// Collect and format CPU information into a `String`.
+    pub fn collect_cpu_info(&self) -> String {
+        format!("processor\t: {}\n", self.processor)
+    }
+}

kernel/src/arch/riscv/signal.rs

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: MPL-2.0
 
-use ostd::cpu::{CpuExceptionInfo, UserContext};
+use ostd::cpu::context::{CpuExceptionInfo, UserContext};
 
 use crate::process::signal::{sig_num::SigNum, signals::fault::FaultSignal, SignalContext};
 

kernel/src/syscall/arch/riscv.rs

@@ -289,7 +289,6 @@ impl_syscall_nums_and_dispatch_fn! {
     SYS_PREADV2 = 286            => sys_preadv2(args[..5]);
     SYS_PWRITEV2 = 287           => sys_pwritev2(args[..5]);
     SYS_STATX = 291              => sys_statx(args[..5]);
-    SYS_PRLIMIT64 = 302          => sys_prlimit64(args[..4]);
     SYS_CLOCK_GETTIME = 403      => sys_clock_gettime(args[..2]);
     SYS_CLOCK_NANOSLEEP = 407    => sys_clock_nanosleep(args[..4]);
     SYS_TIMER_GETTIME = 408      => sys_timer_gettime(args[..2]);