Adjust RISC-V's implementation for recent changes

ostd/src/arch/riscv/mod.rs

@@ -54,6 +54,14 @@ pub fn read_tsc() -> u64 {
     riscv::register::time::read64()
 }
 
+/// Reads a hardware generated 64-bit random value.
+///
+/// Returns None if no random value was generated.
+pub fn read_random() -> Option<u64> {
+    // FIXME: Implement a hardware random number generator on RISC-V platforms.
+    None
+}
+
 pub(crate) fn enable_cpu_features() {
     unsafe {
         riscv::register::sstatus::set_fs(riscv::register::sstatus::FS::Clean);