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Rename various concepts related to memory management
This commit is contained in:
committed by
Tate, Hongliang Tian
parent
03a39c94ca
commit
14e1b1a9fc
@ -9,11 +9,11 @@ use pod::Pod;
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use super::second_stage::{DeviceMode, PageTableEntry, PagingConsts};
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use crate::{
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bus::pci::PciDeviceLocation,
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vm::{
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mm::{
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dma::Daddr,
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page_prop::{CachePolicy, PageProperty, PrivilegedPageFlags as PrivFlags},
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page_table::PageTableError,
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Paddr, PageFlags, PageTable, VmAllocOptions, VmFrame, VmIo, PAGE_SIZE,
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Frame, Paddr, PageFlags, PageTable, VmAllocOptions, VmIo, PAGE_SIZE,
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},
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};
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@ -36,7 +36,7 @@ impl RootEntry {
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pub struct RootTable {
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/// Total 256 bus, each entry is 128 bits.
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root_frame: VmFrame,
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root_frame: Frame,
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// TODO: Use radix tree instead.
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context_tables: BTreeMap<Paddr, ContextTable>,
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}
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@ -233,7 +233,7 @@ pub enum AddressWidth {
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pub struct ContextTable {
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/// Total 32 devices, each device has 8 functions.
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entries_frame: VmFrame,
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entries_frame: Frame,
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page_tables: BTreeMap<Paddr, PageTable<DeviceMode, PageTableEntry, PagingConsts>>,
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}
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