Clarify the usage of ostd::arch

kernel/comps/time/src/rtc/cmos.rs

@@ -2,7 +2,7 @@
 
 use core::sync::atomic::{AtomicU8, Ordering::Relaxed};
 
-use ostd::arch::x86::device::cmos::{century_register, CMOS_ADDRESS, CMOS_DATA};
+use ostd::arch::device::cmos::{century_register, CMOS_ADDRESS, CMOS_DATA};
 
 use crate::SystemTime;
 use super::Driver;

kernel/comps/time/src/rtc/goldfish.rs

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: MPL-2.0
 
-use ostd::{arch::riscv::timer::GOLDFISH_IO_MEM, mm::VmIoOnce};
+use ostd::{arch::timer::GOLDFISH_IO_MEM, mm::VmIoOnce};
 use chrono::{DateTime, Datelike, Timelike};
 
 use crate::{SystemTime, rtc::Driver};

ostd/src/arch/mod.rs

@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: MPL-2.0
-
-//! Platform-specific code.
-//!
-//! Each architecture that Asterinas supports may contain a submodule here.
-
-#[cfg(target_arch = "riscv64")]
-pub mod riscv;
-#[cfg(target_arch = "x86_64")]
-pub mod x86;
-
-#[cfg(target_arch = "riscv64")]
-pub use self::riscv::*;
-#[cfg(target_arch = "x86_64")]
-pub use self::x86::*;

ostd/src/arch/riscv/cpu/context.rs

@@ -6,9 +6,9 @@ use core::fmt::Debug;
 
 use riscv::register::scause::{Exception, Trap};
 
-pub use crate::arch::riscv::trap::GeneralRegs as RawGeneralRegs;
+pub use crate::arch::trap::GeneralRegs as RawGeneralRegs;
 use crate::{
-    arch::riscv::trap::{TrapFrame, UserContext as RawUserContext},
+    arch::trap::{TrapFrame, UserContext as RawUserContext},
     user::{ReturnReason, UserContextApi, UserContextApiInternal},
 };
 

ostd/src/arch/x86/boot/linux_boot/mod.rs

@@ -6,9 +6,9 @@
 use linux_boot_params::{BootParams, E820Type, LINUX_BOOT_HEADER_MAGIC};
 
 #[cfg(feature = "cvm_guest")]
-use crate::arch::x86::init_cvm_guest;
+use crate::arch::init_cvm_guest;
 use crate::{
-    arch::x86::if_tdx_enabled,
+    arch::if_tdx_enabled,
     boot::{
         memory_region::{MemoryRegion, MemoryRegionArray, MemoryRegionType},
         BootloaderAcpiArg, BootloaderFramebufferArg,

ostd/src/arch/x86/boot/smp.rs

@@ -214,7 +214,7 @@ extern "C" {
 unsafe fn wake_up_aps_via_mailbox(num_cpus: u32) {
     use acpi::platform::wakeup_aps;
 
-    use crate::arch::x86::kernel::acpi::AcpiMemoryHandler;
+    use crate::arch::kernel::acpi::AcpiMemoryHandler;
 
     // The symbols are defined in `ap_boot.S`.
     extern "C" {

ostd/src/arch/x86/cpu/context/mod.rs

@@ -23,7 +23,7 @@ use x86_64::registers::{
 };
 
 use crate::{
-    arch::x86::CPU_FEATURES,
+    arch::CPU_FEATURES,
     task::scheduler,
     trap::call_irq_callback_functions,
     user::{ReturnReason, UserContextApi, UserContextApiInternal},
@@ -587,7 +587,7 @@ static XSAVE_AREA_SIZE: Once<usize> = Once::new();
 /// The max size in bytes of the XSAVE area.
 const MAX_XSAVE_AREA_SIZE: usize = 4096;
 
-pub(in crate::arch::x86) fn enable_essential_features() {
+pub(in crate::arch) fn enable_essential_features() {
     XSTATE_MAX_FEATURES.call_once(|| {
         const XSTATE_CPUID: u32 = 0x0000000d;
 

ostd/src/arch/x86/device/cmos.rs

@@ -13,7 +13,7 @@ use acpi::fadt::Fadt;
 use x86_64::instructions::port::{ReadOnlyAccess, WriteOnlyAccess};
 
 use crate::{
-    arch::x86::kernel::acpi::get_acpi_tables,
+    arch::kernel::acpi::get_acpi_tables,
     io::{sensitive_io_port, IoPort},
 };
 

ostd/src/arch/x86/device/serial.rs

@@ -5,7 +5,7 @@
 #![expect(dead_code)]
 
 use crate::{
-    arch::x86::device::io_port::{ReadWriteAccess, WriteOnlyAccess},
+    arch::device::io_port::{ReadWriteAccess, WriteOnlyAccess},
     io::IoPort,
 };
 /// A serial port.

ostd/src/arch/x86/iommu/registers/mod.rs

@@ -37,7 +37,7 @@ use crate::{
                 QUEUE,
             },
         },
-        x86::kernel::acpi::dmar::{Dmar, Remapping},
+        kernel::acpi::dmar::{Dmar, Remapping},
     },
     io::IoMemAllocatorBuilder,
     mm::{paddr_to_vaddr, PAGE_SIZE},

ostd/src/arch/x86/kernel/apic/mod.rs

@@ -348,7 +348,7 @@ pub enum DivideConfig {
 }
 
 pub fn init(io_mem_builder: &IoMemAllocatorBuilder) -> Result<(), ApicInitError> {
-    crate::arch::x86::kernel::pic::disable_temp();
+    crate::arch::kernel::pic::disable_temp();
     if x2apic::X2Apic::has_x2apic() {
         log::info!("x2APIC found!");
         APIC_TYPE.call_once(|| ApicType::X2Apic);

ostd/src/arch/x86/kernel/pic.rs

@@ -7,7 +7,7 @@ use core::sync::atomic::{AtomicBool, AtomicU8, Ordering::Relaxed};
 use log::info;
 
 use crate::{
-    arch::x86::device::io_port::WriteOnlyAccess,
+    arch::device::io_port::WriteOnlyAccess,
     io::{sensitive_io_port, IoPort},
     trap::IrqLine,
 };

ostd/src/arch/x86/kernel/tsc.rs

@@ -19,7 +19,7 @@ use crate::{
 };
 
 /// The frequency of TSC(Hz)
-pub(in crate::arch::x86) static TSC_FREQ: AtomicU64 = AtomicU64::new(0);
+pub(in crate::arch) static TSC_FREQ: AtomicU64 = AtomicU64::new(0);
 
 pub fn init_tsc_freq() {
     let tsc_freq =

ostd/src/arch/x86/timer/hpet.rs

@@ -11,7 +11,7 @@ use volatile::{
 };
 
 use crate::{
-    arch::x86::kernel::{acpi::get_acpi_tables, apic::ioapic},
+    arch::kernel::{acpi::get_acpi_tables, apic::ioapic},
     mm::paddr_to_vaddr,
     trap::IrqLine,
 };

ostd/src/arch/x86/timer/mod.rs

@@ -11,7 +11,7 @@ use core::sync::atomic::Ordering;
 use spin::Once;
 
 use crate::{
-    arch::x86::kernel,
+    arch::kernel,
     cpu::{CpuId, PinCurrentCpu},
     timer::INTERRUPT_CALLBACKS,
     trap::{self, IrqLine, TrapFrame},

ostd/src/arch/x86/timer/pit.rs

@@ -10,7 +10,7 @@
 //!
 
 use crate::{
-    arch::{kernel::IO_APIC, timer::TIMER_FREQ, x86::device::io_port::WriteOnlyAccess},
+    arch::{device::io_port::WriteOnlyAccess, kernel::IO_APIC, timer::TIMER_FREQ},
     io::{sensitive_io_port, IoPort},
     trap::IrqLine,
 };

ostd/src/cpu/mod.rs

@@ -7,10 +7,7 @@ pub mod set;
 
 pub use set::{AtomicCpuSet, CpuSet};
 
-#[cfg(target_arch = "riscv64")]
+pub use crate::arch::cpu::*;
-pub use crate::arch::riscv::cpu::*;
-#[cfg(target_arch = "x86_64")]
-pub use crate::arch::x86::cpu::*;
 use crate::{cpu_local_cell, task::atomic_mode::InAtomicMode};
 
 /// The ID of a CPU in the system.

ostd/src/lib.rs

@@ -25,6 +25,11 @@
 
 extern crate alloc;
 
+#[cfg(target_arch = "x86_64")]
+#[path = "arch/x86/mod.rs"]
+pub mod arch;
+#[cfg(target_arch = "riscv64")]
+#[path = "arch/riscv/mod.rs"]
 pub mod arch;
 pub mod boot;
 pub mod bus;