diff --git a/ostd/src/arch/riscv/timer/mod.rs b/ostd/src/arch/riscv/timer/mod.rs
index 1bbcfe7dd..658fd21b6 100644
--- a/ostd/src/arch/riscv/timer/mod.rs
+++ b/ostd/src/arch/riscv/timer/mod.rs
@@ -8,8 +8,8 @@ use core::{
 };
 
 use crate::{
-    arch::boot::DEVICE_TREE,
-    cpu::{CpuId, PinCurrentCpu},
+    arch::{self, boot::DEVICE_TREE},
+    cpu::{CpuId, IsaExtensions, PinCurrentCpu},
     timer::INTERRUPT_CALLBACKS,
     trap,
 };
@@ -107,10 +107,7 @@ fn set_next_timer_sstc() {
 }
 
 fn is_sstc_enabled() -> bool {
-    let Some(misa) = riscv::register::misa::read() else {
-        return false;
-    };
-    misa.has_extension('S')
+    arch::cpu::has_extensions(IsaExtensions::SSTC)
 }
 
 fn get_next_when() -> u64 {