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Disable RISC-V FPU by default

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Zejun Zhao 2025-03-25 23:43:01 +08:00 committed by Tate, Hongliang Tian
parent 14b8c48859
commit 5630fa8b36
1 changed files with 3 additions and 1 deletions
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4
ostd/src/arch/riscv/mod.rs
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@ -64,6 +64,8 @@ pub fn read_random() -> Option<u64> {
pub(crate) fn enable_cpu_features() { pub(crate) fn enable_cpu_features() {
unsafe { unsafe {
riscv::register::sstatus::set_fs(riscv::register::sstatus::FS::Clean); // We adopt a lazy approach to enable the floating-point unit; it's not
// enabled before the first FPU trap.
riscv::register::sstatus::set_fs(riscv::register::sstatus::FS::Off);
} }
} }