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Extract x86-specific code from call_irq_callback_functions

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This commit is contained in:
YanWQ-monad
2024-07-19 16:45:22 +08:00
committed by Tate, Hongliang Tian
parent b3591131c1
commit 5aa28eae7e
4 changed files with 12 additions and 12 deletions
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2
ostd/src/arch/x86/cpu.rs
View File

@ -324,7 +324,7 @@ impl UserContextApiInternal for UserContext {
} }
} }
}; };
call_irq_callback_functions(&self.as_trap_frame()); call_irq_callback_functions(&self.as_trap_frame(), self.as_trap_frame().trap_num);
if has_kernel_event() { if has_kernel_event() {
return_reason = ReturnReason::KernelEvent; return_reason = ReturnReason::KernelEvent;
break; break;

10
ostd/src/arch/x86/mod.rs
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@ -85,10 +85,12 @@ pub(crate) fn after_all_init() {
kernel::pic::init(); kernel::pic::init();
} }
pub(crate) fn interrupts_ack() { pub(crate) fn interrupts_ack(irq_number: usize) {
kernel::pic::ack(); if !cpu::CpuException::is_cpu_exception(irq_number as u16) {
if let Some(apic) = kernel::apic::APIC_INSTANCE.get() { kernel::pic::ack();
apic.lock_irq_disabled().eoi(); if let Some(apic) = kernel::apic::APIC_INSTANCE.get() {
apic.lock_irq_disabled().eoi();
}
} }
} }

2
ostd/src/arch/x86/trap.rs
View File

@ -65,7 +65,7 @@ extern "sysv64" fn trap_handler(f: &mut TrapFrame) {
} }
} else { } else {
IS_KERNEL_INTERRUPTED.store(true, Ordering::Release); IS_KERNEL_INTERRUPTED.store(true, Ordering::Release);
call_irq_callback_functions(f); call_irq_callback_functions(f, f.trap_num);
IS_KERNEL_INTERRUPTED.store(false, Ordering::Release); IS_KERNEL_INTERRUPTED.store(false, Ordering::Release);
} }
} }

10
ostd/src/trap/handler.rs
View File

@ -4,25 +4,23 @@ use core::sync::atomic::{AtomicBool, Ordering};
use trapframe::TrapFrame; use trapframe::TrapFrame;
use crate::{arch::irq::IRQ_LIST, cpu::CpuException, cpu_local}; use crate::{arch::irq::IRQ_LIST, cpu_local};
pub(crate) fn call_irq_callback_functions(trap_frame: &TrapFrame) { pub(crate) fn call_irq_callback_functions(trap_frame: &TrapFrame, irq_number: usize) {
// For x86 CPUs, interrupts are not re-entrant. Local interrupts will be disabled when // For x86 CPUs, interrupts are not re-entrant. Local interrupts will be disabled when
// an interrupt handler is called (Unless interrupts are re-enabled in an interrupt handler). // an interrupt handler is called (Unless interrupts are re-enabled in an interrupt handler).
// //
// FIXME: For arch that supports re-entrant interrupts, we may need to record nested level here. // FIXME: For arch that supports re-entrant interrupts, we may need to record nested level here.
IN_INTERRUPT_CONTEXT.store(true, Ordering::Release); IN_INTERRUPT_CONTEXT.store(true, Ordering::Release);
let irq_line = IRQ_LIST.get().unwrap().get(trap_frame.trap_num).unwrap(); let irq_line = IRQ_LIST.get().unwrap().get(irq_number).unwrap();
let callback_functions = irq_line.callback_list(); let callback_functions = irq_line.callback_list();
for callback_function in callback_functions.iter() { for callback_function in callback_functions.iter() {
callback_function.call(trap_frame); callback_function.call(trap_frame);
} }
drop(callback_functions); drop(callback_functions);
if !CpuException::is_cpu_exception(trap_frame.trap_num as u16) { crate::arch::interrupts_ack(irq_number);
crate::arch::interrupts_ack();
}
IN_INTERRUPT_CONTEXT.store(false, Ordering::Release); IN_INTERRUPT_CONTEXT.store(false, Ordering::Release);