Add virtio legacy interface

ostd/src/bus/pci/capability/msix.rs

@@ -217,6 +217,12 @@ impl CapabilityMsixData {
     pub fn irq_mut(&mut self, index: usize) -> Option<&mut IrqLine> {
         self.irqs[index].as_mut()
     }
+
+    /// Returns true if MSI-X Enable bit is set.
+    pub fn is_enabled(&self) -> bool {
+        let msg_ctrl = self.loc.read16(self.ptr + 2);
+        msg_ctrl & 0x8000 != 0
+    }
 }
 
 fn set_bit(origin_value: u16, offset: usize, set: bool) -> u16 {

ostd/src/bus/pci/cfg_space.rs

@@ -13,7 +13,10 @@ use super::PciDeviceLocation;
 use crate::{
     arch::device::io_port::{PortRead, PortWrite},
     io_mem::IoMem,
-    mm::page_prop::{CachePolicy, PageFlags},
+    mm::{
+        page_prop::{CachePolicy, PageFlags},
+        PodOnce, VmIoOnce,
+    },
     Error, Result,
 };
 
@@ -175,6 +178,22 @@ impl Bar {
             Self::Io(Arc::new(IoBar::new(&location, index)?))
         })
     }
+
+    /// Reads a value of a specified type at a specified offset.
+    pub fn read_once<T: PodOnce + PortRead>(&self, offset: usize) -> Result<T> {
+        match self {
+            Bar::Memory(mem_bar) => mem_bar.io_mem().read_once(offset),
+            Bar::Io(io_bar) => io_bar.read(offset as u32),
+        }
+    }
+
+    /// Writes a value of a specified type at a specified offset.
+    pub fn write_once<T: PodOnce + PortWrite>(&self, offset: usize, value: T) -> Result<()> {
+        match self {
+            Bar::Memory(mem_bar) => mem_bar.io_mem().write_once(offset, &value),
+            Bar::Io(io_bar) => io_bar.write(offset as u32, value),
+        }
+    }
 }
 
 /// Memory BAR