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Add missing TLB flushes for the kernel stack guard pages

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Zhang Junyang
2024-06-27 08:39:37 +00:00
committed by Tate, Hongliang Tian
parent 57ecfa2fec
commit 8cd8cf3938
2 changed files with 14 additions and 6 deletions
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7
ostd/src/arch/x86/mm/mod.rs
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@ -63,20 +63,27 @@ bitflags::bitflags! {
}
}
/// Flush any TLB entry that contains the map of the given virtual address.
///
/// This flush performs regardless of the global-page bit. So it can flush both global
/// and non-global entries.
pub(crate) fn tlb_flush_addr(vaddr: Vaddr) {
tlb::flush(VirtAddr::new(vaddr as u64));
}
/// Flush any TLB entry that intersects with the given address range.
pub(crate) fn tlb_flush_addr_range(range: &Range<Vaddr>) {
for vaddr in range.clone().step_by(PAGE_SIZE) {
tlb_flush_addr(vaddr);
}
}
/// Flush all TLB entries except for the global-page entries.
pub(crate) fn tlb_flush_all_excluding_global() {
tlb::flush_all();
}
/// Flush all TLB entries, including global-page entries.
pub(crate) fn tlb_flush_all_including_global() {
// SAFETY: updates to CR4 here only change the global-page bit, the side effect
// is only to invalidate the TLB, which doesn't affect the memory safety.