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Fix compile error in riscv64
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@ -151,7 +151,7 @@ impl DmaStream {
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if self.inner.is_cache_coherent {
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return Ok(());
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}
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let start_va = self.inner.vm_segment.as_ptr();
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let start_va = crate::mm::paddr_to_vaddr(self.inner.vm_segment.paddr()) as *const u8;
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// TODO: Query the CPU for the cache line size via CPUID, we use 64 bytes as the cache line size here.
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for i in _byte_range.step_by(64) {
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// TODO: Call the cache line flush command in the corresponding architecture.
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