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Fix compile error in riscv64

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Yuke Peng 2024-10-18 21:56:48 +08:00 committed by Tate, Hongliang Tian
parent 2f511069ee
commit a43b0b6a52
1 changed files with 1 additions and 1 deletions
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2
ostd/src/mm/dma/dma_stream.rs
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@ -151,7 +151,7 @@ impl DmaStream {
if self.inner.is_cache_coherent {
return Ok(());
}
let start_va = self.inner.vm_segment.as_ptr();
let start_va = crate::mm::paddr_to_vaddr(self.inner.vm_segment.paddr()) as *const u8;
// TODO: Query the CPU for the cache line size via CPUID, we use 64 bytes as the cache line size here.
for i in _byte_range.step_by(64) {
// TODO: Call the cache line flush command in the corresponding architecture.