mirror of
https://github.com/asterinas/asterinas.git
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Use tdx-guest crate VE handler and support release mode for TDX
This commit is contained in:
Hsy-Intel
Tate, Hongliang Tian
parent
7527d20d25
commit
a739b3828d
@ -41,7 +41,7 @@ smoltcp = { version = "0.9.1", default-features = false, features = [
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"socket-raw",
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"socket-dhcpv4",
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] }
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tdx-guest = { version = "0.1.5", optional = true }
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tdx-guest = { version = "0.1.7", optional = true }
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# parse elf file
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xmas-elf = "0.8.0"
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@ -8,7 +8,6 @@ use crate::{
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error::Error,
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events::IoEvents,
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fs::{inode_handle::FileIo, utils::IoctlCmd},
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prelude::*,
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process::signal::Poller,
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};
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@ -57,7 +57,7 @@ iced-x86 = { version = "1.21.0", default-features = false, features = [
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"decoder",
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"gas",
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], optional = true }
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tdx-guest = { version = "0.1.5", optional = true }
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tdx-guest = { version = "0.1.7", optional = true }
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[features]
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default = ["cvm_guest", "log_color"]
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@ -23,8 +23,9 @@ use crate::{
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cfg_if! {
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if #[cfg(feature = "cvm_guest")] {
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use tdx_guest::tdcall;
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use crate::arch::tdx_guest::{handle_virtual_exception, TdxTrapFrame};
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mod tdx;
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use tdx::handle_virtualization_exception;
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}
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}
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@ -49,106 +50,6 @@ pub struct CpuExceptionInfo {
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pub page_fault_addr: usize,
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}
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#[cfg(feature = "cvm_guest")]
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impl TdxTrapFrame for RawGeneralRegs {
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fn rax(&self) -> usize {
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self.rax
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}
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fn set_rax(&mut self, rax: usize) {
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self.rax = rax;
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}
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fn rbx(&self) -> usize {
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self.rbx
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}
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fn set_rbx(&mut self, rbx: usize) {
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self.rbx = rbx;
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}
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fn rcx(&self) -> usize {
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self.rcx
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}
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fn set_rcx(&mut self, rcx: usize) {
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self.rcx = rcx;
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}
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fn rdx(&self) -> usize {
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self.rdx
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}
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fn set_rdx(&mut self, rdx: usize) {
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self.rdx = rdx;
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}
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fn rsi(&self) -> usize {
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self.rsi
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}
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fn set_rsi(&mut self, rsi: usize) {
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self.rsi = rsi;
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}
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fn rdi(&self) -> usize {
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self.rdi
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}
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fn set_rdi(&mut self, rdi: usize) {
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self.rdi = rdi;
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}
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fn rip(&self) -> usize {
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self.rip
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}
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fn set_rip(&mut self, rip: usize) {
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self.rip = rip;
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}
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fn r8(&self) -> usize {
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self.r8
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}
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fn set_r8(&mut self, r8: usize) {
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self.r8 = r8;
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}
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fn r9(&self) -> usize {
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self.r9
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}
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fn set_r9(&mut self, r9: usize) {
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self.r9 = r9;
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}
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fn r10(&self) -> usize {
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self.r10
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}
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fn set_r10(&mut self, r10: usize) {
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self.r10 = r10;
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}
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fn r11(&self) -> usize {
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self.r11
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}
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fn set_r11(&mut self, r11: usize) {
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self.r11 = r11;
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}
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fn r12(&self) -> usize {
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self.r12
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}
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fn set_r12(&mut self, r12: usize) {
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self.r12 = r12;
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}
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fn r13(&self) -> usize {
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self.r13
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}
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fn set_r13(&mut self, r13: usize) {
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self.r13 = r13;
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}
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fn r14(&self) -> usize {
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self.r14
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}
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fn set_r14(&mut self, r14: usize) {
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self.r14 = r14;
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}
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fn r15(&self) -> usize {
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self.r15
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}
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fn set_r15(&mut self, r15: usize) {
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self.r15 = r15;
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}
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fn rbp(&self) -> usize {
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self.rbp
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}
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fn set_rbp(&mut self, rbp: usize) {
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self.rbp = rbp;
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}
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}
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/// User Preemption.
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pub struct UserPreemption {
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count: u32,
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@ -222,9 +123,7 @@ impl UserContextApiInternal for UserContext {
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Some(exception) => {
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#[cfg(feature = "cvm_guest")]
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if *exception == VIRTUALIZATION_EXCEPTION {
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let ve_info =
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tdcall::get_veinfo().expect("#VE handler: fail to get VE info\n");
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handle_virtual_exception(self.general_regs_mut(), &ve_info);
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handle_virtualization_exception(self);
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continue;
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}
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if exception.typ == CpuExceptionType::FaultOrTrap
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113
ostd/src/arch/x86/cpu/tdx.rs
Normal file
113
ostd/src/arch/x86/cpu/tdx.rs
Normal file
@ -0,0 +1,113 @@
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// SPDX-License-Identifier: MPL-2.0
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use tdx_guest::{handle_virtual_exception as do_handle_virtual_exception, tdcall, TdxTrapFrame};
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use crate::cpu::{RawGeneralRegs, UserContext};
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pub(crate) fn handle_virtualization_exception(user_context: &mut UserContext) {
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let ve_info = tdcall::get_veinfo().expect("#VE handler: fail to get VE info\n");
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let mut generalrags_wrapper = GeneralRegsWrapper(&mut *user_context.general_regs_mut());
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do_handle_virtual_exception(&mut generalrags_wrapper, &ve_info);
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*user_context.general_regs_mut() = *generalrags_wrapper.0;
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}
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struct GeneralRegsWrapper<'a>(&'a mut RawGeneralRegs);
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impl TdxTrapFrame for GeneralRegsWrapper<'_> {
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fn rax(&self) -> usize {
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self.0.rax
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}
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fn set_rax(&mut self, rax: usize) {
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self.0.rax = rax;
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}
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fn rbx(&self) -> usize {
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self.0.rbx
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}
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fn set_rbx(&mut self, rbx: usize) {
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self.0.rbx = rbx;
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}
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fn rcx(&self) -> usize {
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self.0.rcx
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}
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fn set_rcx(&mut self, rcx: usize) {
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self.0.rcx = rcx;
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}
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fn rdx(&self) -> usize {
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self.0.rdx
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}
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fn set_rdx(&mut self, rdx: usize) {
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self.0.rdx = rdx;
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}
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fn rsi(&self) -> usize {
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self.0.rsi
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}
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fn set_rsi(&mut self, rsi: usize) {
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self.0.rsi = rsi;
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}
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fn rdi(&self) -> usize {
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self.0.rdi
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}
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fn set_rdi(&mut self, rdi: usize) {
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self.0.rdi = rdi;
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}
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fn rip(&self) -> usize {
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self.0.rip
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}
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fn set_rip(&mut self, rip: usize) {
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self.0.rip = rip;
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}
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fn r8(&self) -> usize {
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self.0.r8
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}
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fn set_r8(&mut self, r8: usize) {
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self.0.r8 = r8;
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}
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fn r9(&self) -> usize {
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self.0.r9
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}
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fn set_r9(&mut self, r9: usize) {
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self.0.r9 = r9;
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}
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fn r10(&self) -> usize {
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self.0.r10
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}
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fn set_r10(&mut self, r10: usize) {
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self.0.r10 = r10;
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}
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fn r11(&self) -> usize {
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self.0.r11
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}
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fn set_r11(&mut self, r11: usize) {
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self.0.r11 = r11;
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}
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fn r12(&self) -> usize {
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self.0.r12
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}
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fn set_r12(&mut self, r12: usize) {
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self.0.r12 = r12;
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}
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fn r13(&self) -> usize {
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self.0.r13
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}
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fn set_r13(&mut self, r13: usize) {
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self.0.r13 = r13;
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}
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fn r14(&self) -> usize {
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self.0.r14
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}
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fn set_r14(&mut self, r14: usize) {
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self.0.r14 = r14;
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}
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fn r15(&self) -> usize {
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self.0.r15
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}
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fn set_r15(&mut self, r15: usize) {
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self.0.r15 = r15;
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}
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fn rbp(&self) -> usize {
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self.0.rbp
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}
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fn set_rbp(&mut self, rbp: usize) {
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self.0.rbp = rbp;
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}
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}
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@ -1,19 +1,12 @@
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// SPDX-License-Identifier: MPL-2.0
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use iced_x86::{Code, Decoder, DecoderOptions, Instruction, Register};
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use log::warn;
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use tdx_guest::{
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serial_println, tdcall,
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tdcall::{accept_page, TdgVeInfo},
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tdvmcall,
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tdvmcall::{cpuid, hlt, map_gpa, rdmsr, read_mmio, write_mmio, wrmsr, IoSize},
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TdxVirtualExceptionType,
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};
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use tdx_guest::{tdcall::accept_page, tdvmcall::map_gpa, TdxTrapFrame};
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use trapframe::TrapFrame;
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use crate::{
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mm::{
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kspace::{BOOT_PAGE_TABLE, KERNEL_BASE_VADDR, KERNEL_END_VADDR, KERNEL_PAGE_TABLE},
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kspace::{BOOT_PAGE_TABLE, KERNEL_PAGE_TABLE},
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paddr_to_vaddr,
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page_prop::{PageProperty, PrivilegedPageFlags as PrivFlags},
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PAGE_SIZE,
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@ -24,62 +17,6 @@ use crate::{
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const SHARED_BIT: u8 = 51;
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const SHARED_MASK: u64 = 1u64 << SHARED_BIT;
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// Intel TDX guest physical address. Maybe protected(private) gpa or unprotected(shared) gpa.
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pub type TdxGpa = usize;
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pub trait TdxTrapFrame {
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fn rax(&self) -> usize;
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fn set_rax(&mut self, rax: usize);
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fn rbx(&self) -> usize;
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fn set_rbx(&mut self, rbx: usize);
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fn rcx(&self) -> usize;
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fn set_rcx(&mut self, rcx: usize);
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fn rdx(&self) -> usize;
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fn set_rdx(&mut self, rdx: usize);
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fn rsi(&self) -> usize;
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fn set_rsi(&mut self, rsi: usize);
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fn rdi(&self) -> usize;
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fn set_rdi(&mut self, rdi: usize);
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fn rip(&self) -> usize;
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fn set_rip(&mut self, rip: usize);
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fn r8(&self) -> usize;
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fn set_r8(&mut self, r8: usize);
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fn r9(&self) -> usize;
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fn set_r9(&mut self, r9: usize);
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fn r10(&self) -> usize;
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fn set_r10(&mut self, r10: usize);
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fn r11(&self) -> usize;
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fn set_r11(&mut self, r11: usize);
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fn r12(&self) -> usize;
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fn set_r12(&mut self, r12: usize);
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fn r13(&self) -> usize;
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fn set_r13(&mut self, r13: usize);
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fn r14(&self) -> usize;
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fn set_r14(&mut self, r14: usize);
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fn r15(&self) -> usize;
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fn set_r15(&mut self, r15: usize);
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fn rbp(&self) -> usize;
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fn set_rbp(&mut self, rbp: usize);
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}
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enum InstrMmioType {
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Write,
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WriteImm,
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Read,
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ReadZeroExtend,
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ReadSignExtend,
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Movs,
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}
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#[derive(Debug)]
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enum MmioError {
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Unimplemented,
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InvalidInstruction,
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InvalidAddress,
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DecodeFailed,
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TdVmcallError,
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}
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#[derive(Debug)]
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pub enum PageConvertError {
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PageTable,
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@ -87,313 +24,6 @@ pub enum PageConvertError {
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TdVmcall,
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}
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pub fn handle_virtual_exception(trapframe: &mut dyn TdxTrapFrame, ve_info: &TdgVeInfo) {
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let mut instr_len = ve_info.exit_instruction_length;
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match ve_info.exit_reason.into() {
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TdxVirtualExceptionType::Hlt => {
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serial_println!("Ready to halt");
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hlt();
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}
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TdxVirtualExceptionType::Io => {
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if !handle_io(trapframe, ve_info) {
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serial_println!("Handle tdx ioexit errors, ready to halt");
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hlt();
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}
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}
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TdxVirtualExceptionType::MsrRead => {
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let msr = unsafe { rdmsr(trapframe.rcx() as u32).unwrap() };
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trapframe.set_rax((msr as u32 & u32::MAX) as usize);
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trapframe.set_rdx(((msr >> 32) as u32 & u32::MAX) as usize);
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}
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TdxVirtualExceptionType::MsrWrite => {
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let data = trapframe.rax() as u64 | ((trapframe.rdx() as u64) << 32);
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unsafe { wrmsr(trapframe.rcx() as u32, data).unwrap() };
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}
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TdxVirtualExceptionType::CpuId => {
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let cpuid_info = cpuid(trapframe.rax() as u32, trapframe.rcx() as u32).unwrap();
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let mask = 0xFFFF_FFFF_0000_0000_usize;
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trapframe.set_rax((trapframe.rax() & mask) | cpuid_info.eax);
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trapframe.set_rbx((trapframe.rbx() & mask) | cpuid_info.ebx);
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trapframe.set_rcx((trapframe.rcx() & mask) | cpuid_info.ecx);
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trapframe.set_rdx((trapframe.rdx() & mask) | cpuid_info.edx);
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}
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TdxVirtualExceptionType::EptViolation => {
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if is_protected_gpa(ve_info.guest_physical_address as TdxGpa) {
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serial_println!("Unexpected EPT-violation on private memory");
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hlt();
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}
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instr_len = handle_mmio(trapframe, ve_info).unwrap() as u32;
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}
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TdxVirtualExceptionType::Other => {
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serial_println!("Unknown TDX vitrual exception type");
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hlt();
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}
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_ => return,
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}
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trapframe.set_rip(trapframe.rip() + instr_len as usize);
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}
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fn handle_io(trapframe: &mut dyn TdxTrapFrame, ve_info: &tdcall::TdgVeInfo) -> bool {
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let size = match ve_info.exit_qualification & 0x3 {
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0 => IoSize::Size1,
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1 => IoSize::Size2,
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3 => IoSize::Size4,
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_ => panic!("Invalid size value"),
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};
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let direction = if (ve_info.exit_qualification >> 3) & 0x1 == 0 {
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tdvmcall::Direction::Out
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} else {
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tdvmcall::Direction::In
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};
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let _operand = if (ve_info.exit_qualification >> 6) & 0x1 == 0 {
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tdvmcall::Operand::Dx
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} else {
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tdvmcall::Operand::Immediate
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};
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let port = (ve_info.exit_qualification >> 16) as u16;
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match direction {
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tdvmcall::Direction::In => {
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trapframe.set_rax(tdvmcall::io_read(size, port).unwrap() as usize);
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}
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tdvmcall::Direction::Out => {
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tdvmcall::io_write(size, port, trapframe.rax() as u32).unwrap();
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}
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};
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true
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}
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fn is_protected_gpa(gpa: TdxGpa) -> bool {
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(gpa as u64 & SHARED_MASK) == 0
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}
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fn handle_mmio(trapframe: &mut dyn TdxTrapFrame, ve_info: &TdgVeInfo) -> Result<usize, MmioError> {
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// Get instruction
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let instr = decode_instr(trapframe.rip())?;
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// Decode MMIO instruction
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match decode_mmio(&instr) {
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Some((mmio, size)) => {
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match mmio {
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InstrMmioType::Write => {
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let value = match instr.op1_register() {
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Register::RCX => trapframe.rcx() as u64,
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Register::ECX => (trapframe.rcx() & 0xFFFF_FFFF) as u64,
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Register::CX => (trapframe.rcx() & 0xFFFF) as u64,
|
||||
Register::CL => (trapframe.rcx() & 0xFF) as u64,
|
||||
_ => todo!(),
|
||||
};
|
||||
// SAFETY: The mmio_gpa obtained from `ve_info` is valid, and the value and size parsed from the instruction are valid.
|
||||
unsafe {
|
||||
write_mmio(size, ve_info.guest_physical_address, value)
|
||||
.map_err(|_| MmioError::TdVmcallError)?
|
||||
}
|
||||
}
|
||||
InstrMmioType::WriteImm => {
|
||||
let value = instr.immediate(0);
|
||||
// SAFETY: The mmio_gpa obtained from `ve_info` is valid, and the value and size parsed from the instruction are valid.
|
||||
unsafe {
|
||||
write_mmio(size, ve_info.guest_physical_address, value)
|
||||
.map_err(|_| MmioError::TdVmcallError)?
|
||||
}
|
||||
}
|
||||
InstrMmioType::Read =>
|
||||
// SAFETY: The mmio_gpa obtained from `ve_info` is valid, and the size parsed from the instruction is valid.
|
||||
unsafe {
|
||||
let read_res = read_mmio(size, ve_info.guest_physical_address)
|
||||
.map_err(|_| MmioError::TdVmcallError)?
|
||||
as usize;
|
||||
match instr.op0_register() {
|
||||
Register::RAX => trapframe.set_rax(read_res),
|
||||
Register::EAX => {
|
||||
trapframe.set_rax((trapframe.rax() & 0xFFFF_FFFF_0000_0000) | read_res)
|
||||
}
|
||||
Register::AX => {
|
||||
trapframe.set_rax((trapframe.rax() & 0xFFFF_FFFF_FFFF_0000) | read_res)
|
||||
}
|
||||
Register::AL => {
|
||||
trapframe.set_rax((trapframe.rax() & 0xFFFF_FFFF_FFFF_FF00) | read_res)
|
||||
}
|
||||
Register::RBX => trapframe.set_rbx(read_res),
|
||||
Register::EBX => {
|
||||
trapframe.set_rbx((trapframe.rbx() & 0xFFFF_FFFF_0000_0000) | read_res)
|
||||
}
|
||||
Register::BX => {
|
||||
trapframe.set_rbx((trapframe.rbx() & 0xFFFF_FFFF_FFFF_0000) | read_res)
|
||||
}
|
||||
Register::BL => {
|
||||
trapframe.set_rbx((trapframe.rbx() & 0xFFFF_FFFF_FFFF_FF00) | read_res)
|
||||
}
|
||||
Register::RCX => trapframe.set_rcx(read_res),
|
||||
Register::ECX => {
|
||||
trapframe.set_rcx((trapframe.rcx() & 0xFFFF_FFFF_0000_0000) | read_res)
|
||||
}
|
||||
Register::CX => {
|
||||
trapframe.set_rcx((trapframe.rcx() & 0xFFFF_FFFF_FFFF_0000) | read_res)
|
||||
}
|
||||
Register::CL => {
|
||||
trapframe.set_rcx((trapframe.rcx() & 0xFFFF_FFFF_FFFF_FF00) | read_res)
|
||||
}
|
||||
Register::RDX => trapframe.set_rdx(read_res),
|
||||
Register::EDX => {
|
||||
trapframe.set_rdx((trapframe.rdx() & 0xFFFF_FFFF_0000_0000) | read_res)
|
||||
}
|
||||
Register::DX => {
|
||||
trapframe.set_rdx((trapframe.rdx() & 0xFFFF_FFFF_FFFF_0000) | read_res)
|
||||
}
|
||||
Register::DL => {
|
||||
trapframe.set_rdx((trapframe.rdx() & 0xFFFF_FFFF_FFFF_FF00) | read_res)
|
||||
}
|
||||
Register::SIL => {
|
||||
trapframe.set_rsi((trapframe.rsi() & 0xFFFF_FFFF_FFFF_FF00) | read_res)
|
||||
}
|
||||
Register::DIL => {
|
||||
trapframe.set_rdi((trapframe.rdi() & 0xFFFF_FFFF_FFFF_FF00) | read_res)
|
||||
}
|
||||
Register::R8L => {
|
||||
trapframe.set_r8((trapframe.r8() & 0xFFFF_FFFF_FFFF_FF00) | read_res)
|
||||
}
|
||||
Register::R9L => {
|
||||
trapframe.set_r9((trapframe.r9() & 0xFFFF_FFFF_FFFF_FF00) | read_res)
|
||||
}
|
||||
Register::R10L => {
|
||||
trapframe.set_r10((trapframe.r10() & 0xFFFF_FFFF_FFFF_FF00) | read_res)
|
||||
}
|
||||
Register::R11L => {
|
||||
trapframe.set_r11((trapframe.r11() & 0xFFFF_FFFF_FFFF_FF00) | read_res)
|
||||
}
|
||||
Register::R11W => {
|
||||
trapframe.set_r11((trapframe.r11() & 0xFFFF_FFFF_FFFF_0000) | read_res)
|
||||
}
|
||||
Register::R12L => {
|
||||
trapframe.set_r12((trapframe.r12() & 0xFFFF_FFFF_FFFF_FF00) | read_res)
|
||||
}
|
||||
Register::R13L => {
|
||||
trapframe.set_r13((trapframe.r13() & 0xFFFF_FFFF_FFFF_FF00) | read_res)
|
||||
}
|
||||
Register::R13W => {
|
||||
trapframe.set_r13((trapframe.r13() & 0xFFFF_FFFF_FFFF_0000) | read_res)
|
||||
}
|
||||
Register::R14L => {
|
||||
trapframe.set_r14((trapframe.r14() & 0xFFFF_FFFF_FFFF_FF00) | read_res)
|
||||
}
|
||||
Register::R14D => {
|
||||
trapframe.set_r14((trapframe.r14() & 0xFFFF_FFFF_0000_0000) | read_res)
|
||||
}
|
||||
Register::R15L => {
|
||||
trapframe.set_r15((trapframe.r15() & 0xFFFF_FFFF_FFFF_FF00) | read_res)
|
||||
}
|
||||
Register::BP => {
|
||||
trapframe.set_rbp((trapframe.rbp() & 0xFFFF_FFFF_FFFF_0000) | read_res)
|
||||
}
|
||||
Register::BPL => {
|
||||
trapframe.set_rbp((trapframe.rbp() & 0xFFFF_FFFF_FFFF_FF00) | read_res)
|
||||
}
|
||||
_ => return Err(MmioError::Unimplemented),
|
||||
}
|
||||
},
|
||||
InstrMmioType::ReadZeroExtend =>
|
||||
// SAFETY: The mmio_gpa obtained from `ve_info` is valid, and the size parsed from the instruction is valid.
|
||||
unsafe {
|
||||
let read_res = read_mmio(size, ve_info.guest_physical_address)
|
||||
.map_err(|_| MmioError::TdVmcallError)?
|
||||
as usize;
|
||||
match instr.op0_register() {
|
||||
Register::RAX | Register::EAX | Register::AX | Register::AL => {
|
||||
trapframe.set_rax(read_res)
|
||||
}
|
||||
Register::RBX | Register::EBX | Register::BX | Register::BL => {
|
||||
trapframe.set_rbx(read_res)
|
||||
}
|
||||
Register::RCX | Register::ECX | Register::CX | Register::CL => {
|
||||
trapframe.set_rcx(read_res)
|
||||
}
|
||||
_ => return Err(MmioError::Unimplemented),
|
||||
}
|
||||
},
|
||||
InstrMmioType::ReadSignExtend => return Err(MmioError::Unimplemented),
|
||||
// MMIO was accessed with an instruction that could not be decoded or handled properly.
|
||||
InstrMmioType::Movs => return Err(MmioError::InvalidInstruction),
|
||||
}
|
||||
}
|
||||
None => {
|
||||
return Err(MmioError::DecodeFailed);
|
||||
}
|
||||
}
|
||||
Ok(instr.len())
|
||||
}
|
||||
|
||||
fn decode_instr(rip: usize) -> Result<Instruction, MmioError> {
|
||||
if !(KERNEL_BASE_VADDR..KERNEL_END_VADDR).contains(&rip) {
|
||||
return Err(MmioError::InvalidAddress);
|
||||
}
|
||||
let code_data = {
|
||||
const MAX_X86_INSTR_LEN: usize = 15;
|
||||
let mut data = [0u8; MAX_X86_INSTR_LEN];
|
||||
// SAFETY:
|
||||
// This is safe because we are ensuring that 'rip' is a valid kernel virtual address before this operation.
|
||||
// We are also ensuring that the size of the data we are copying does not exceed 'MAX_X86_INSTR_LEN'.
|
||||
// Therefore, we are not reading any memory that we shouldn't be, and we are not causing any undefined behavior.
|
||||
unsafe {
|
||||
core::ptr::copy_nonoverlapping(rip as *const u8, data.as_mut_ptr(), data.len());
|
||||
}
|
||||
data
|
||||
};
|
||||
let mut decoder = Decoder::with_ip(64, &code_data, rip as u64, DecoderOptions::NONE);
|
||||
let mut instr = Instruction::default();
|
||||
decoder.decode_out(&mut instr);
|
||||
if instr.is_invalid() {
|
||||
return Err(MmioError::InvalidInstruction);
|
||||
}
|
||||
Ok(instr)
|
||||
}
|
||||
|
||||
fn decode_mmio(instr: &Instruction) -> Option<(InstrMmioType, IoSize)> {
|
||||
match instr.code() {
|
||||
// 0x88
|
||||
Code::Mov_rm8_r8 => Some((InstrMmioType::Write, IoSize::Size1)),
|
||||
// 0x89
|
||||
Code::Mov_rm16_r16 => Some((InstrMmioType::Write, IoSize::Size2)),
|
||||
Code::Mov_rm32_r32 => Some((InstrMmioType::Write, IoSize::Size4)),
|
||||
Code::Mov_rm64_r64 => Some((InstrMmioType::Write, IoSize::Size8)),
|
||||
// 0xc6
|
||||
Code::Mov_rm8_imm8 => Some((InstrMmioType::WriteImm, IoSize::Size1)),
|
||||
// 0xc7
|
||||
Code::Mov_rm16_imm16 => Some((InstrMmioType::WriteImm, IoSize::Size2)),
|
||||
Code::Mov_rm32_imm32 => Some((InstrMmioType::WriteImm, IoSize::Size4)),
|
||||
Code::Mov_rm64_imm32 => Some((InstrMmioType::WriteImm, IoSize::Size8)),
|
||||
// 0x8a
|
||||
Code::Mov_r8_rm8 => Some((InstrMmioType::Read, IoSize::Size1)),
|
||||
// 0x8b
|
||||
Code::Mov_r16_rm16 => Some((InstrMmioType::Read, IoSize::Size2)),
|
||||
Code::Mov_r32_rm32 => Some((InstrMmioType::Read, IoSize::Size4)),
|
||||
Code::Mov_r64_rm64 => Some((InstrMmioType::Read, IoSize::Size8)),
|
||||
// 0xa4
|
||||
Code::Movsb_m8_m8 => Some((InstrMmioType::Movs, IoSize::Size1)),
|
||||
// 0xa5
|
||||
Code::Movsw_m16_m16 => Some((InstrMmioType::Movs, IoSize::Size2)),
|
||||
Code::Movsd_m32_m32 => Some((InstrMmioType::Movs, IoSize::Size4)),
|
||||
Code::Movsq_m64_m64 => Some((InstrMmioType::Movs, IoSize::Size8)),
|
||||
// 0x0f 0xb6
|
||||
Code::Movzx_r16_rm8 | Code::Movzx_r32_rm8 | Code::Movzx_r64_rm8 => {
|
||||
Some((InstrMmioType::ReadZeroExtend, IoSize::Size1))
|
||||
}
|
||||
// 0x0f 0xb7
|
||||
Code::Movzx_r16_rm16 | Code::Movzx_r32_rm16 | Code::Movzx_r64_rm16 => {
|
||||
Some((InstrMmioType::ReadZeroExtend, IoSize::Size2))
|
||||
}
|
||||
// 0x0f 0xbe
|
||||
Code::Movsx_r16_rm8 | Code::Movsx_r32_rm8 | Code::Movsx_r64_rm8 => {
|
||||
Some((InstrMmioType::ReadSignExtend, IoSize::Size1))
|
||||
}
|
||||
// 0x0f 0xbf
|
||||
Code::Movsx_r16_rm16 | Code::Movsx_r32_rm16 | Code::Movsx_r64_rm16 => {
|
||||
Some((InstrMmioType::ReadSignExtend, IoSize::Size2))
|
||||
}
|
||||
_ => None,
|
||||
}
|
||||
}
|
||||
|
||||
/// Sets the given physical address range to Intel TDX shared pages.
|
||||
/// Clears the data within the given address range.
|
||||
/// Make sure the provided physical address is page size aligned.
|
||||
@ -484,102 +114,104 @@ pub unsafe fn protect_gpa_range(gpa: Paddr, page_num: usize) -> Result<(), PageC
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub struct TrapFrameWrapper<'a>(pub &'a mut TrapFrame);
|
||||
|
||||
#[cfg(feature = "cvm_guest")]
|
||||
impl TdxTrapFrame for TrapFrame {
|
||||
impl TdxTrapFrame for TrapFrameWrapper<'_> {
|
||||
fn rax(&self) -> usize {
|
||||
self.rax
|
||||
self.0.rax
|
||||
}
|
||||
fn set_rax(&mut self, rax: usize) {
|
||||
self.rax = rax;
|
||||
self.0.rax = rax;
|
||||
}
|
||||
fn rbx(&self) -> usize {
|
||||
self.rbx
|
||||
self.0.rbx
|
||||
}
|
||||
fn set_rbx(&mut self, rbx: usize) {
|
||||
self.rbx = rbx;
|
||||
self.0.rbx = rbx;
|
||||
}
|
||||
fn rcx(&self) -> usize {
|
||||
self.rcx
|
||||
self.0.rcx
|
||||
}
|
||||
fn set_rcx(&mut self, rcx: usize) {
|
||||
self.rcx = rcx;
|
||||
self.0.rcx = rcx;
|
||||
}
|
||||
fn rdx(&self) -> usize {
|
||||
self.rdx
|
||||
self.0.rdx
|
||||
}
|
||||
fn set_rdx(&mut self, rdx: usize) {
|
||||
self.rdx = rdx;
|
||||
self.0.rdx = rdx;
|
||||
}
|
||||
fn rsi(&self) -> usize {
|
||||
self.rsi
|
||||
self.0.rsi
|
||||
}
|
||||
fn set_rsi(&mut self, rsi: usize) {
|
||||
self.rsi = rsi;
|
||||
self.0.rsi = rsi;
|
||||
}
|
||||
fn rdi(&self) -> usize {
|
||||
self.rdi
|
||||
self.0.rdi
|
||||
}
|
||||
fn set_rdi(&mut self, rdi: usize) {
|
||||
self.rdi = rdi;
|
||||
self.0.rdi = rdi;
|
||||
}
|
||||
fn rip(&self) -> usize {
|
||||
self.rip
|
||||
self.0.rip
|
||||
}
|
||||
fn set_rip(&mut self, rip: usize) {
|
||||
self.rip = rip;
|
||||
self.0.rip = rip;
|
||||
}
|
||||
fn r8(&self) -> usize {
|
||||
self.r8
|
||||
self.0.r8
|
||||
}
|
||||
fn set_r8(&mut self, r8: usize) {
|
||||
self.r8 = r8;
|
||||
self.0.r8 = r8;
|
||||
}
|
||||
fn r9(&self) -> usize {
|
||||
self.r9
|
||||
self.0.r9
|
||||
}
|
||||
fn set_r9(&mut self, r9: usize) {
|
||||
self.r9 = r9;
|
||||
self.0.r9 = r9;
|
||||
}
|
||||
fn r10(&self) -> usize {
|
||||
self.r10
|
||||
self.0.r10
|
||||
}
|
||||
fn set_r10(&mut self, r10: usize) {
|
||||
self.r10 = r10;
|
||||
self.0.r10 = r10;
|
||||
}
|
||||
fn r11(&self) -> usize {
|
||||
self.r11
|
||||
self.0.r11
|
||||
}
|
||||
fn set_r11(&mut self, r11: usize) {
|
||||
self.r11 = r11;
|
||||
self.0.r11 = r11;
|
||||
}
|
||||
fn r12(&self) -> usize {
|
||||
self.r12
|
||||
self.0.r12
|
||||
}
|
||||
fn set_r12(&mut self, r12: usize) {
|
||||
self.r12 = r12;
|
||||
self.0.r12 = r12;
|
||||
}
|
||||
fn r13(&self) -> usize {
|
||||
self.r13
|
||||
self.0.r13
|
||||
}
|
||||
fn set_r13(&mut self, r13: usize) {
|
||||
self.r13 = r13;
|
||||
self.0.r13 = r13;
|
||||
}
|
||||
fn r14(&self) -> usize {
|
||||
self.r14
|
||||
self.0.r14
|
||||
}
|
||||
fn set_r14(&mut self, r14: usize) {
|
||||
self.r14 = r14;
|
||||
self.0.r14 = r14;
|
||||
}
|
||||
fn r15(&self) -> usize {
|
||||
self.r15
|
||||
self.0.r15
|
||||
}
|
||||
fn set_r15(&mut self, r15: usize) {
|
||||
self.r15 = r15;
|
||||
self.0.r15 = r15;
|
||||
}
|
||||
fn rbp(&self) -> usize {
|
||||
self.rbp
|
||||
self.0.rbp
|
||||
}
|
||||
fn set_rbp(&mut self, rbp: usize) {
|
||||
self.rbp = rbp;
|
||||
self.0.rbp = rbp;
|
||||
}
|
||||
}
|
||||
|
||||
@ -22,8 +22,8 @@ use crate::{
|
||||
|
||||
cfg_if! {
|
||||
if #[cfg(feature = "cvm_guest")] {
|
||||
use tdx_guest::{tdcall, tdx_is_enabled};
|
||||
use crate::arch::{cpu::VIRTUALIZATION_EXCEPTION, tdx_guest::handle_virtual_exception};
|
||||
use tdx_guest::{tdcall, tdx_is_enabled, handle_virtual_exception};
|
||||
use crate::arch::{cpu::VIRTUALIZATION_EXCEPTION, tdx_guest::TrapFrameWrapper};
|
||||
}
|
||||
}
|
||||
|
||||
@ -46,7 +46,9 @@ extern "sysv64" fn trap_handler(f: &mut TrapFrame) {
|
||||
#[cfg(feature = "cvm_guest")]
|
||||
&VIRTUALIZATION_EXCEPTION => {
|
||||
let ve_info = tdcall::get_veinfo().expect("#VE handler: fail to get VE info\n");
|
||||
handle_virtual_exception(f, &ve_info);
|
||||
let mut trapframe_wrapper = TrapFrameWrapper(&mut *f);
|
||||
handle_virtual_exception(&mut trapframe_wrapper, &ve_info);
|
||||
*f = *trapframe_wrapper.0;
|
||||
}
|
||||
&PAGE_FAULT => {
|
||||
let page_fault_addr = x86_64::registers::control::Cr2::read().as_u64();
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user