From b097060c5ed9903d73bcf4c92726e47c650d12bc Mon Sep 17 00:00:00 2001
From: Zejun Zhao <jelly.zhao.42@gmail.com>
Date: Tue, 25 Mar 2025 23:23:33 +0800
Subject: [PATCH] Clean up RISC-V-specific boot code

---
 ostd/src/arch/riscv/boot/mod.rs | 40 ++++++++++++++++++++-------------
 ostd/src/arch/riscv/trap/mod.rs |  2 +-
 2 files changed, 25 insertions(+), 17 deletions(-)

diff --git a/ostd/src/arch/riscv/boot/mod.rs b/ostd/src/arch/riscv/boot/mod.rs
index d88524526..8917ed673 100644
--- a/ostd/src/arch/riscv/boot/mod.rs
+++ b/ostd/src/arch/riscv/boot/mod.rs
@@ -42,10 +42,12 @@ fn parse_initramfs() -> Option<&'static [u8]> {
 }
 
 fn parse_acpi_arg() -> BootloaderAcpiArg {
+    // TDDO: Add ACPI support for RISC-V, maybe.
     BootloaderAcpiArg::NotProvided
 }
 
 fn parse_framebuffer_info() -> Option<BootloaderFramebufferArg> {
+    // TODO: Parse framebuffer info from device tree.
     None
 }
 
@@ -54,11 +56,13 @@ fn parse_memory_regions() -> MemoryRegionArray {
 
     for region in DEVICE_TREE.get().unwrap().memory().regions() {
         if region.size.unwrap_or(0) > 0 {
-            regions.push(MemoryRegion::new(
-                region.starting_address as usize,
-                region.size.unwrap(),
-                MemoryRegionType::Usable,
-            ));
+            regions
+                .push(MemoryRegion::new(
+                    region.starting_address as usize,
+                    region.size.unwrap(),
+                    MemoryRegionType::Usable,
+                ))
+                .unwrap();
         }
     }
 
@@ -66,26 +70,30 @@ fn parse_memory_regions() -> MemoryRegionArray {
         for child in node.children() {
             if let Some(reg_iter) = child.reg() {
                 for region in reg_iter {
-                    regions.push(MemoryRegion::new(
-                        region.starting_address as usize,
-                        region.size.unwrap(),
-                        MemoryRegionType::Reserved,
-                    ));
+                    regions
+                        .push(MemoryRegion::new(
+                            region.starting_address as usize,
+                            region.size.unwrap(),
+                            MemoryRegionType::Reserved,
+                        ))
+                        .unwrap();
                 }
             }
         }
     }
 
     // Add the kernel region.
-    regions.push(MemoryRegion::kernel());
+    regions.push(MemoryRegion::kernel()).unwrap();
 
     // Add the initramfs region.
     if let Some((start, end)) = parse_initramfs_range() {
-        regions.push(MemoryRegion::new(
-            start,
-            end - start,
-            MemoryRegionType::Module,
-        ));
+        regions
+            .push(MemoryRegion::new(
+                start,
+                end - start,
+                MemoryRegionType::Module,
+            ))
+            .unwrap();
     }
 
     regions.into_non_overlapping()
diff --git a/ostd/src/arch/riscv/trap/mod.rs b/ostd/src/arch/riscv/trap/mod.rs
index 7cdb94785..3c347e1fe 100644
--- a/ostd/src/arch/riscv/trap/mod.rs
+++ b/ostd/src/arch/riscv/trap/mod.rs
@@ -13,7 +13,7 @@ cpu_local_cell! {
 }
 
 /// Initialize interrupt handling on RISC-V.
-pub unsafe fn init(on_bsp: bool) {
+pub unsafe fn init(_on_bsp: bool) {
     self::trap::init();
 }