From b96c8f9ed2220f3ad59ceb470132c8a218c6ce27 Mon Sep 17 00:00:00 2001 From: Ruihan Li Date: Wed, 16 Apr 2025 20:27:14 +0800 Subject: [PATCH] Make `ostd::trap::irq` public --- kernel/comps/softirq/src/lib.rs | 5 ++++- kernel/comps/softirq/src/lock.rs | 2 +- kernel/comps/softirq/src/taskless.rs | 6 +++--- .../virtio/src/transport/mmio/bus/common_device.rs | 4 ++-- kernel/comps/virtio/src/transport/mmio/bus/mod.rs | 2 +- kernel/comps/virtio/src/transport/mmio/device.rs | 2 +- .../comps/virtio/src/transport/mmio/multiplex.rs | 5 ++++- kernel/comps/virtio/src/transport/mod.rs | 2 +- kernel/comps/virtio/src/transport/pci/device.rs | 2 +- kernel/comps/virtio/src/transport/pci/legacy.rs | 2 +- kernel/comps/virtio/src/transport/pci/msix.rs | 4 ++-- kernel/src/sched/sched_class/mod.rs | 2 +- osdk/deps/frame-allocator/src/cache.rs | 2 +- osdk/deps/frame-allocator/src/lib.rs | 6 +++--- osdk/deps/frame-allocator/src/pools/mod.rs | 2 +- osdk/deps/frame-allocator/src/smp_counter.rs | 2 +- osdk/deps/heap-allocator/src/allocator.rs | 4 ++-- osdk/deps/test-kernel/src/lib.rs | 2 +- ostd/src/arch/riscv/timer/mod.rs | 2 +- ostd/src/arch/x86/iommu/fault.rs | 2 +- ostd/src/arch/x86/kernel/apic/x2apic.rs | 2 +- ostd/src/arch/x86/kernel/apic/xapic.rs | 2 +- ostd/src/arch/x86/kernel/irq/ioapic.rs | 2 +- ostd/src/arch/x86/kernel/irq/mod.rs | 2 +- ostd/src/arch/x86/kernel/tsc.rs | 2 +- ostd/src/arch/x86/timer/apic.rs | 2 +- ostd/src/arch/x86/timer/hpet.rs | 2 +- ostd/src/arch/x86/timer/mod.rs | 4 ++-- ostd/src/arch/x86/timer/pit.rs | 2 +- ostd/src/bus/pci/capability/msix.rs | 2 +- ostd/src/cpu/local/cell.rs | 2 +- ostd/src/cpu/local/dyn_cpu_local.rs | 2 +- ostd/src/cpu/local/mod.rs | 6 +++--- ostd/src/cpu/local/single_instr.rs | 14 +++++++------- ostd/src/cpu/local/static_cpu_local.rs | 4 ++-- ostd/src/mm/tlb.rs | 2 +- ostd/src/panic.rs | 2 +- ostd/src/smp.rs | 4 ++-- ostd/src/sync/guard.rs | 2 +- ostd/src/task/kernel_stack.rs | 2 +- ostd/src/task/processor.rs | 4 ++-- ostd/src/timer/mod.rs | 2 +- ostd/src/trap/handler.rs | 2 +- ostd/src/trap/irq.rs | 7 +++++-- ostd/src/trap/mod.rs | 5 ++--- 45 files changed, 75 insertions(+), 67 deletions(-) diff --git a/kernel/comps/softirq/src/lib.rs b/kernel/comps/softirq/src/lib.rs index c0945a41d..b43cd66c6 100644 --- a/kernel/comps/softirq/src/lib.rs +++ b/kernel/comps/softirq/src/lib.rs @@ -13,7 +13,10 @@ use component::{init_component, ComponentInitError}; use lock::is_softirq_enabled; use ostd::{ cpu_local_cell, - trap::{disable_local, register_bottom_half_handler, DisabledLocalIrqGuard}, + trap::{ + irq::{disable_local, DisabledLocalIrqGuard}, + register_bottom_half_handler, + }, }; use spin::Once; diff --git a/kernel/comps/softirq/src/lock.rs b/kernel/comps/softirq/src/lock.rs index 12dd472ff..25c23e099 100644 --- a/kernel/comps/softirq/src/lock.rs +++ b/kernel/comps/softirq/src/lock.rs @@ -7,7 +7,7 @@ use ostd::{ atomic_mode::{AsAtomicModeGuard, InAtomicMode}, disable_preempt, DisabledPreemptGuard, }, - trap::{disable_local, in_interrupt_context}, + trap::{in_interrupt_context, irq::disable_local}, }; use crate::process_all_pending; diff --git a/kernel/comps/softirq/src/taskless.rs b/kernel/comps/softirq/src/taskless.rs index 03a35e80f..14b9ce398 100644 --- a/kernel/comps/softirq/src/taskless.rs +++ b/kernel/comps/softirq/src/taskless.rs @@ -131,7 +131,7 @@ fn do_schedule( { return; } - let irq_guard = trap::disable_local(); + let irq_guard = trap::irq::disable_local(); taskless_list .get_with(&irq_guard) .borrow_mut() @@ -158,7 +158,7 @@ fn taskless_softirq_handler( softirq_id: u8, ) { let mut processing_list = { - let irq_guard = trap::disable_local(); + let irq_guard = trap::irq::disable_local(); let guard = taskless_list.get_with(&irq_guard); let mut list_mut = guard.borrow_mut(); LinkedList::take(list_mut.deref_mut()) @@ -170,7 +170,7 @@ fn taskless_softirq_handler( .compare_exchange(false, true, Ordering::Acquire, Ordering::Relaxed) .is_err() { - let irq_guard = trap::disable_local(); + let irq_guard = trap::irq::disable_local(); taskless_list .get_with(&irq_guard) .borrow_mut() diff --git a/kernel/comps/virtio/src/transport/mmio/bus/common_device.rs b/kernel/comps/virtio/src/transport/mmio/bus/common_device.rs index 552a2f918..18afab0dc 100644 --- a/kernel/comps/virtio/src/transport/mmio/bus/common_device.rs +++ b/kernel/comps/virtio/src/transport/mmio/bus/common_device.rs @@ -7,8 +7,8 @@ use log::info; #[cfg(target_arch = "x86_64")] use ostd::arch::kernel::MappedIrqLine; #[cfg(target_arch = "riscv64")] // TODO: Add `MappedIrqLine` support for RISC-V. -use ostd::trap::IrqLine as MappedIrqLine; -use ostd::{io::IoMem, mm::VmIoOnce, trap::IrqLine, Error, Result}; +use ostd::trap::irq::IrqLine as MappedIrqLine; +use ostd::{io::IoMem, mm::VmIoOnce, trap::irq::IrqLine, Error, Result}; /// A MMIO common device. #[derive(Debug)] diff --git a/kernel/comps/virtio/src/transport/mmio/bus/mod.rs b/kernel/comps/virtio/src/transport/mmio/bus/mod.rs index db5a9a43e..c79c2cf40 100644 --- a/kernel/comps/virtio/src/transport/mmio/bus/mod.rs +++ b/kernel/comps/virtio/src/transport/mmio/bus/mod.rs @@ -28,7 +28,7 @@ pub(super) fn init() { fn x86_probe() { use common_device::{mmio_check_magic, mmio_read_device_id, MmioCommonDevice}; use log::debug; - use ostd::{arch::kernel::IRQ_CHIP, io::IoMem, trap::IrqLine}; + use ostd::{arch::kernel::IRQ_CHIP, io::IoMem, trap::irq::IrqLine}; // TODO: The correct method for detecting VirtIO-MMIO devices on x86_64 systems is to parse the // kernel command line if ACPI tables are absent [1], or the ACPI SSDT if ACPI tables are diff --git a/kernel/comps/virtio/src/transport/mmio/device.rs b/kernel/comps/virtio/src/transport/mmio/device.rs index cf0bc8bc1..1b700d32b 100644 --- a/kernel/comps/virtio/src/transport/mmio/device.rs +++ b/kernel/comps/virtio/src/transport/mmio/device.rs @@ -11,7 +11,7 @@ use ostd::{ io::IoMem, mm::{DmaCoherent, PAGE_SIZE}, sync::RwLock, - trap::IrqCallbackFunction, + trap::irq::IrqCallbackFunction, }; use super::{ diff --git a/kernel/comps/virtio/src/transport/mmio/multiplex.rs b/kernel/comps/virtio/src/transport/mmio/multiplex.rs index fb97345d9..6e372447e 100644 --- a/kernel/comps/virtio/src/transport/mmio/multiplex.rs +++ b/kernel/comps/virtio/src/transport/mmio/multiplex.rs @@ -8,7 +8,10 @@ use aster_util::safe_ptr::SafePtr; use ostd::{ io::IoMem, sync::RwLock, - trap::{IrqCallbackFunction, IrqLine, TrapFrame}, + trap::{ + irq::{IrqCallbackFunction, IrqLine}, + TrapFrame, + }, }; /// Multiplexing Irqs. The two interrupt types (configuration space change and queue interrupt) diff --git a/kernel/comps/virtio/src/transport/mod.rs b/kernel/comps/virtio/src/transport/mod.rs index 794457d16..0e4e388c1 100644 --- a/kernel/comps/virtio/src/transport/mod.rs +++ b/kernel/comps/virtio/src/transport/mod.rs @@ -9,7 +9,7 @@ use ostd::{ bus::pci::cfg_space::Bar, io::IoMem, mm::{DmaCoherent, PodOnce}, - trap::IrqCallbackFunction, + trap::irq::IrqCallbackFunction, Pod, }; diff --git a/kernel/comps/virtio/src/transport/pci/device.rs b/kernel/comps/virtio/src/transport/pci/device.rs index 9e30e0dcb..be8eeb2be 100644 --- a/kernel/comps/virtio/src/transport/pci/device.rs +++ b/kernel/comps/virtio/src/transport/pci/device.rs @@ -15,7 +15,7 @@ use ostd::{ }, io::IoMem, mm::DmaCoherent, - trap::IrqCallbackFunction, + trap::irq::IrqCallbackFunction, }; use super::{common_cfg::VirtioPciCommonCfg, msix::VirtioMsixManager}; diff --git a/kernel/comps/virtio/src/transport/pci/legacy.rs b/kernel/comps/virtio/src/transport/pci/legacy.rs index 08e177b4e..fa8a8647b 100644 --- a/kernel/comps/virtio/src/transport/pci/legacy.rs +++ b/kernel/comps/virtio/src/transport/pci/legacy.rs @@ -12,7 +12,7 @@ use ostd::{ }, io::IoMem, mm::{DmaCoherent, HasDaddr, PAGE_SIZE}, - trap::IrqCallbackFunction, + trap::irq::IrqCallbackFunction, }; use crate::{ diff --git a/kernel/comps/virtio/src/transport/pci/msix.rs b/kernel/comps/virtio/src/transport/pci/msix.rs index c732fb994..11ebed479 100644 --- a/kernel/comps/virtio/src/transport/pci/msix.rs +++ b/kernel/comps/virtio/src/transport/pci/msix.rs @@ -2,7 +2,7 @@ use alloc::vec::Vec; -use ostd::{bus::pci::capability::msix::CapabilityMsixData, trap::IrqLine}; +use ostd::{bus::pci::capability::msix::CapabilityMsixData, trap::irq::IrqLine}; pub struct VirtioMsixManager { config_msix_vector: u16, @@ -20,7 +20,7 @@ impl VirtioMsixManager { pub fn new(mut msix: CapabilityMsixData) -> Self { let mut msix_vector_list: Vec = (0..msix.table_size()).collect(); for i in msix_vector_list.iter() { - let irq = ostd::trap::IrqLine::alloc().unwrap(); + let irq = IrqLine::alloc().unwrap(); msix.set_interrupt_vector(irq, *i); } let config_msix_vector = msix_vector_list.pop().unwrap(); diff --git a/kernel/src/sched/sched_class/mod.rs b/kernel/src/sched/sched_class/mod.rs index 654bc85f8..6f933923b 100644 --- a/kernel/src/sched/sched_class/mod.rs +++ b/kernel/src/sched/sched_class/mod.rs @@ -16,7 +16,7 @@ use ostd::{ }, AtomicCpuId, Task, }, - trap::disable_local, + trap::irq::disable_local, }; use super::{ diff --git a/osdk/deps/frame-allocator/src/cache.rs b/osdk/deps/frame-allocator/src/cache.rs index 6aa26bc81..ff05bdcb8 100644 --- a/osdk/deps/frame-allocator/src/cache.rs +++ b/osdk/deps/frame-allocator/src/cache.rs @@ -7,7 +7,7 @@ use core::{alloc::Layout, cell::RefCell}; use ostd::{ cpu_local, mm::{Paddr, PAGE_SIZE}, - trap::DisabledLocalIrqGuard, + trap::irq::DisabledLocalIrqGuard, }; cpu_local! { diff --git a/osdk/deps/frame-allocator/src/lib.rs b/osdk/deps/frame-allocator/src/lib.rs index d91f9c3ea..e309adb68 100644 --- a/osdk/deps/frame-allocator/src/lib.rs +++ b/osdk/deps/frame-allocator/src/lib.rs @@ -64,7 +64,7 @@ pub struct FrameAllocator; impl GlobalFrameAllocator for FrameAllocator { fn alloc(&self, layout: Layout) -> Option { - let guard = trap::disable_local(); + let guard = trap::irq::disable_local(); let res = cache::alloc(&guard, layout); if res.is_some() { TOTAL_FREE_SIZE.sub(guard.current_cpu(), layout.size()); @@ -73,13 +73,13 @@ impl GlobalFrameAllocator for FrameAllocator { } fn dealloc(&self, addr: Paddr, size: usize) { - let guard = trap::disable_local(); + let guard = trap::irq::disable_local(); TOTAL_FREE_SIZE.add(guard.current_cpu(), size); cache::dealloc(&guard, addr, size); } fn add_free_memory(&self, addr: Paddr, size: usize) { - let guard = trap::disable_local(); + let guard = trap::irq::disable_local(); TOTAL_FREE_SIZE.add(guard.current_cpu(), size); pools::add_free_memory(&guard, addr, size); } diff --git a/osdk/deps/frame-allocator/src/pools/mod.rs b/osdk/deps/frame-allocator/src/pools/mod.rs index e01561cd8..bae6b9da6 100644 --- a/osdk/deps/frame-allocator/src/pools/mod.rs +++ b/osdk/deps/frame-allocator/src/pools/mod.rs @@ -13,7 +13,7 @@ use ostd::{ cpu_local, mm::Paddr, sync::{LocalIrqDisabled, SpinLock, SpinLockGuard}, - trap::DisabledLocalIrqGuard, + trap::irq::DisabledLocalIrqGuard, }; use crate::chunk::{greater_order_of, lesser_order_of, size_of_order, split_to_chunks, BuddyOrder}; diff --git a/osdk/deps/frame-allocator/src/smp_counter.rs b/osdk/deps/frame-allocator/src/smp_counter.rs index ef63e2ba3..f1eec178f 100644 --- a/osdk/deps/frame-allocator/src/smp_counter.rs +++ b/osdk/deps/frame-allocator/src/smp_counter.rs @@ -98,7 +98,7 @@ mod test { pub static FREE_SIZE_COUNTER: usize; } - let guard = trap::disable_local(); + let guard = trap::irq::disable_local(); let cur_cpu = guard.current_cpu(); FREE_SIZE_COUNTER.add(cur_cpu, 10); assert_eq!(FREE_SIZE_COUNTER.get(), 10); diff --git a/osdk/deps/heap-allocator/src/allocator.rs b/osdk/deps/heap-allocator/src/allocator.rs index 1db3392c9..07ba54458 100644 --- a/osdk/deps/heap-allocator/src/allocator.rs +++ b/osdk/deps/heap-allocator/src/allocator.rs @@ -296,7 +296,7 @@ impl GlobalHeapAllocator for HeapAllocator { return HeapSlot::alloc_large(layout.size().div_ceil(PAGE_SIZE) * PAGE_SIZE); }; - let irq_guard = trap::disable_local(); + let irq_guard = trap::irq::disable_local(); let this_cache = LOCAL_POOL.get_with(&irq_guard); let mut local_cache = this_cache.borrow_mut(); @@ -309,7 +309,7 @@ impl GlobalHeapAllocator for HeapAllocator { return Ok(()); }; - let irq_guard = trap::disable_local(); + let irq_guard = trap::irq::disable_local(); let this_cache = LOCAL_POOL.get_with(&irq_guard); let mut local_cache = this_cache.borrow_mut(); diff --git a/osdk/deps/test-kernel/src/lib.rs b/osdk/deps/test-kernel/src/lib.rs index ff2ecbfd8..922b9e99f 100644 --- a/osdk/deps/test-kernel/src/lib.rs +++ b/osdk/deps/test-kernel/src/lib.rs @@ -54,7 +54,7 @@ fn main() { #[ostd::ktest::panic_handler] fn panic_handler(info: &core::panic::PanicInfo) -> ! { - let _irq_guard = ostd::trap::disable_local(); + let _irq_guard = ostd::trap::irq::disable_local(); use alloc::{boxed::Box, string::ToString}; diff --git a/ostd/src/arch/riscv/timer/mod.rs b/ostd/src/arch/riscv/timer/mod.rs index 658fd21b6..873050a78 100644 --- a/ostd/src/arch/riscv/timer/mod.rs +++ b/ostd/src/arch/riscv/timer/mod.rs @@ -67,7 +67,7 @@ pub(super) unsafe fn init() { } pub(super) fn handle_timer_interrupt() { - let irq_guard = trap::disable_local(); + let irq_guard = trap::irq::disable_local(); if irq_guard.current_cpu() == CpuId::bsp() { crate::timer::jiffies::ELAPSED.fetch_add(1, Ordering::Relaxed); } diff --git a/ostd/src/arch/x86/iommu/fault.rs b/ostd/src/arch/x86/iommu/fault.rs index 77b2b6618..dccebb2e4 100644 --- a/ostd/src/arch/x86/iommu/fault.rs +++ b/ostd/src/arch/x86/iommu/fault.rs @@ -11,7 +11,7 @@ use volatile::{access::ReadWrite, VolatileRef}; use super::registers::Capability; use crate::{ sync::{LocalIrqDisabled, SpinLock}, - trap::{IrqLine, TrapFrame}, + trap::{irq::IrqLine, TrapFrame}, }; #[derive(Debug)] diff --git a/ostd/src/arch/x86/kernel/apic/x2apic.rs b/ostd/src/arch/x86/kernel/apic/x2apic.rs index eb18fdcc8..3727bf19c 100644 --- a/ostd/src/arch/x86/kernel/apic/x2apic.rs +++ b/ostd/src/arch/x86/kernel/apic/x2apic.rs @@ -76,7 +76,7 @@ impl super::Apic for X2Apic { } unsafe fn send_ipi(&self, icr: super::Icr) { - let _guard = crate::trap::disable_local(); + let _guard = crate::trap::irq::disable_local(); // SAFETY: These `rdmsr` and `wrmsr` instructions write the interrupt command to APIC and // wait for results. The caller guarantees it's safe to execute this interrupt command. unsafe { diff --git a/ostd/src/arch/x86/kernel/apic/xapic.rs b/ostd/src/arch/x86/kernel/apic/xapic.rs index 53da387cd..d0d7d7663 100644 --- a/ostd/src/arch/x86/kernel/apic/xapic.rs +++ b/ostd/src/arch/x86/kernel/apic/xapic.rs @@ -79,7 +79,7 @@ impl super::Apic for XApic { } unsafe fn send_ipi(&self, icr: super::Icr) { - let _guard = crate::trap::disable_local(); + let _guard = crate::trap::irq::disable_local(); self.write(xapic::XAPIC_ESR, 0); // The upper 32 bits of ICR must be written into XAPIC_ICR1 first, // because writing into XAPIC_ICR0 will trigger the action of diff --git a/ostd/src/arch/x86/kernel/irq/ioapic.rs b/ostd/src/arch/x86/kernel/irq/ioapic.rs index e61c59248..502da8add 100644 --- a/ostd/src/arch/x86/kernel/irq/ioapic.rs +++ b/ostd/src/arch/x86/kernel/irq/ioapic.rs @@ -11,7 +11,7 @@ use volatile::{ }; use crate::{ - arch::if_tdx_enabled, io::IoMemAllocatorBuilder, mm::paddr_to_vaddr, trap::IrqLine, Error, + arch::if_tdx_enabled, io::IoMemAllocatorBuilder, mm::paddr_to_vaddr, trap::irq::IrqLine, Error, Result, }; diff --git a/ostd/src/arch/x86/kernel/irq/mod.rs b/ostd/src/arch/x86/kernel/irq/mod.rs index c0d91bc23..62043d5a5 100644 --- a/ostd/src/arch/x86/kernel/irq/mod.rs +++ b/ostd/src/arch/x86/kernel/irq/mod.rs @@ -11,7 +11,7 @@ use log::info; use spin::Once; use super::acpi::get_acpi_tables; -use crate::{io::IoMemAllocatorBuilder, sync::SpinLock, trap::IrqLine, Error, Result}; +use crate::{io::IoMemAllocatorBuilder, sync::SpinLock, trap::irq::IrqLine, Error, Result}; mod ioapic; mod pic; diff --git a/ostd/src/arch/x86/kernel/tsc.rs b/ostd/src/arch/x86/kernel/tsc.rs index c8bd204c5..e2500bde6 100644 --- a/ostd/src/arch/x86/kernel/tsc.rs +++ b/ostd/src/arch/x86/kernel/tsc.rs @@ -12,7 +12,7 @@ use crate::{ pit::{self, OperatingMode}, TIMER_FREQ, }, - trap::{IrqLine, TrapFrame}, + trap::{irq::IrqLine, TrapFrame}, }; /// The frequency of TSC(Hz) diff --git a/ostd/src/arch/x86/timer/apic.rs b/ostd/src/arch/x86/timer/apic.rs index b1b155ff7..fdfc8818b 100644 --- a/ostd/src/arch/x86/timer/apic.rs +++ b/ostd/src/arch/x86/timer/apic.rs @@ -12,7 +12,7 @@ use crate::{ tsc_freq, }, task::disable_preempt, - trap::{IrqLine, TrapFrame}, + trap::{irq::IrqLine, TrapFrame}, }; /// Initializes APIC with TSC-deadline mode or periodic mode. diff --git a/ostd/src/arch/x86/timer/hpet.rs b/ostd/src/arch/x86/timer/hpet.rs index 74101a2d8..0f1acd285 100644 --- a/ostd/src/arch/x86/timer/hpet.rs +++ b/ostd/src/arch/x86/timer/hpet.rs @@ -13,7 +13,7 @@ use volatile::{ use crate::{ arch::kernel::{acpi::get_acpi_tables, MappedIrqLine, IRQ_CHIP}, mm::paddr_to_vaddr, - trap::IrqLine, + trap::irq::IrqLine, }; static HPET_INSTANCE: Once = Once::new(); diff --git a/ostd/src/arch/x86/timer/mod.rs b/ostd/src/arch/x86/timer/mod.rs index b741a0469..62711c1d8 100644 --- a/ostd/src/arch/x86/timer/mod.rs +++ b/ostd/src/arch/x86/timer/mod.rs @@ -14,7 +14,7 @@ use crate::{ arch::kernel, cpu::{CpuId, PinCurrentCpu}, timer::INTERRUPT_CALLBACKS, - trap::{self, IrqLine, TrapFrame}, + trap::{self, irq::IrqLine, TrapFrame}, }; /// The timer frequency (Hz). @@ -61,7 +61,7 @@ pub(super) fn init_ap() { } fn timer_callback(_: &TrapFrame) { - let irq_guard = trap::disable_local(); + let irq_guard = trap::irq::disable_local(); if irq_guard.current_cpu() == CpuId::bsp() { crate::timer::jiffies::ELAPSED.fetch_add(1, Ordering::SeqCst); } diff --git a/ostd/src/arch/x86/timer/pit.rs b/ostd/src/arch/x86/timer/pit.rs index 35c6f67dd..064019ada 100644 --- a/ostd/src/arch/x86/timer/pit.rs +++ b/ostd/src/arch/x86/timer/pit.rs @@ -16,7 +16,7 @@ use crate::{ timer::TIMER_FREQ, }, io::{sensitive_io_port, IoPort}, - trap::IrqLine, + trap::irq::IrqLine, }; /// PIT Operating Mode. diff --git a/ostd/src/bus/pci/capability/msix.rs b/ostd/src/bus/pci/capability/msix.rs index fb4d1444c..f1bed9fce 100644 --- a/ostd/src/bus/pci/capability/msix.rs +++ b/ostd/src/bus/pci/capability/msix.rs @@ -15,7 +15,7 @@ use crate::{ device_info::PciDeviceLocation, }, mm::VmIoOnce, - trap::IrqLine, + trap::irq::IrqLine, }; /// MSI-X capability. It will set the BAR space it uses to be hidden. diff --git a/ostd/src/cpu/local/cell.rs b/ostd/src/cpu/local/cell.rs index 872e549bf..442d2701a 100644 --- a/ostd/src/cpu/local/cell.rs +++ b/ostd/src/cpu/local/cell.rs @@ -33,7 +33,7 @@ use crate::arch; /// // You can avoid this by disabling interrupts (and preemption, if needed). /// println!("BAR VAL: {:?}", BAR.load()); /// -/// let _irq_guard = ostd::trap::disable_local_irq(); +/// let _irq_guard = ostd::trap::irq::disable_local_irq(); /// println!("1st FOO VAL: {:?}", FOO.load()); /// // No surprises here, the two accesses must result in the same value. /// println!("2nd FOO VAL: {:?}", FOO.load()); diff --git a/ostd/src/cpu/local/dyn_cpu_local.rs b/ostd/src/cpu/local/dyn_cpu_local.rs index aa2a495ee..da29376fe 100644 --- a/ostd/src/cpu/local/dyn_cpu_local.rs +++ b/ostd/src/cpu/local/dyn_cpu_local.rs @@ -10,7 +10,7 @@ use super::{AnyStorage, CpuLocal}; use crate::{ cpu::{all_cpus, num_cpus, CpuId, PinCurrentCpu}, mm::{paddr_to_vaddr, FrameAllocOptions, Segment, Vaddr, PAGE_SIZE}, - trap::DisabledLocalIrqGuard, + trap::irq::DisabledLocalIrqGuard, Result, }; diff --git a/ostd/src/cpu/local/mod.rs b/ostd/src/cpu/local/mod.rs index 1a57007fd..d7607c5f6 100644 --- a/ostd/src/cpu/local/mod.rs +++ b/ostd/src/cpu/local/mod.rs @@ -56,7 +56,7 @@ use static_cpu_local::StaticStorage; use super::CpuId; use crate::{ mm::{frame::allocator, paddr_to_vaddr, Paddr, PAGE_SIZE}, - trap::DisabledLocalIrqGuard, + trap::irq::DisabledLocalIrqGuard, }; /// Dynamically-allocated CPU-local objects. @@ -324,7 +324,7 @@ mod test { crate::cpu_local! { static FOO: RefCell = RefCell::new(1); } - let irq_guard = crate::trap::disable_local(); + let irq_guard = crate::trap::irq::disable_local(); let foo_guard = FOO.get_with(&irq_guard); assert_eq!(*foo_guard.borrow(), 1); *foo_guard.borrow_mut() = 2; @@ -337,7 +337,7 @@ mod test { crate::cpu_local_cell! { static BAR: usize = 3; } - let _guard = crate::trap::disable_local(); + let _guard = crate::trap::irq::disable_local(); assert_eq!(BAR.load(), 3); BAR.store(4); assert_eq!(BAR.load(), 4); diff --git a/ostd/src/cpu/local/single_instr.rs b/ostd/src/cpu/local/single_instr.rs index f61bc6315..59370ee22 100644 --- a/ostd/src/cpu/local/single_instr.rs +++ b/ostd/src/cpu/local/single_instr.rs @@ -41,7 +41,7 @@ pub trait SingleInstructionAddAssign { impl SingleInstructionAddAssign for T { default unsafe fn add_assign(offset: *mut Self, rhs: T) { - let _guard = crate::trap::disable_local(); + let _guard = crate::trap::irq::disable_local(); let base = crate::arch::cpu::local::get_base() as usize; let addr = (base + offset as usize) as *mut Self; // SAFETY: @@ -67,7 +67,7 @@ pub trait SingleInstructionSubAssign { impl SingleInstructionSubAssign for T { default unsafe fn sub_assign(offset: *mut Self, rhs: T) { - let _guard = crate::trap::disable_local(); + let _guard = crate::trap::irq::disable_local(); let base = crate::arch::cpu::local::get_base() as usize; let addr = (base + offset as usize) as *mut Self; // SAFETY: Same as `add_assign`. @@ -87,7 +87,7 @@ pub trait SingleInstructionBitOrAssign { impl + Copy> SingleInstructionBitOrAssign for T { default unsafe fn bitor_assign(offset: *mut Self, rhs: T) { - let _guard = crate::trap::disable_local(); + let _guard = crate::trap::irq::disable_local(); let base = crate::arch::cpu::local::get_base() as usize; let addr = (base + offset as usize) as *mut Self; // SAFETY: Same as `add_assign`. @@ -107,7 +107,7 @@ pub trait SingleInstructionBitAndAssign { impl + Copy> SingleInstructionBitAndAssign for T { default unsafe fn bitand_assign(offset: *mut Self, rhs: T) { - let _guard = crate::trap::disable_local(); + let _guard = crate::trap::irq::disable_local(); let base = crate::arch::cpu::local::get_base() as usize; let addr = (base + offset as usize) as *mut Self; // SAFETY: Same as `add_assign`. @@ -127,7 +127,7 @@ pub trait SingleInstructionBitXorAssign { impl + Copy> SingleInstructionBitXorAssign for T { default unsafe fn bitxor_assign(offset: *mut Self, rhs: T) { - let _guard = crate::trap::disable_local(); + let _guard = crate::trap::irq::disable_local(); let base = crate::arch::cpu::local::get_base() as usize; let addr = (base + offset as usize) as *mut Self; // SAFETY: Same as `add_assign`. @@ -147,7 +147,7 @@ pub trait SingleInstructionLoad { impl SingleInstructionLoad for T { default unsafe fn load(offset: *const Self) -> Self { - let _guard = crate::trap::disable_local(); + let _guard = crate::trap::irq::disable_local(); let base = crate::arch::cpu::local::get_base() as usize; let ptr = (base + offset as usize) as *const Self; // SAFETY: Same as `add_assign`. @@ -167,7 +167,7 @@ pub trait SingleInstructionStore { impl SingleInstructionStore for T { default unsafe fn store(offset: *mut Self, val: Self) { - let _guard = crate::trap::disable_local(); + let _guard = crate::trap::irq::disable_local(); let base = crate::arch::cpu::local::get_base() as usize; let ptr = (base + offset as usize) as *mut Self; // SAFETY: Same as `add_assign`. diff --git a/ostd/src/cpu/local/static_cpu_local.rs b/ostd/src/cpu/local/static_cpu_local.rs index 68f54bdd6..1a3127f41 100644 --- a/ostd/src/cpu/local/static_cpu_local.rs +++ b/ostd/src/cpu/local/static_cpu_local.rs @@ -5,7 +5,7 @@ use core::marker::PhantomData; use super::{AnyStorage, CpuLocal, __cpu_local_end, __cpu_local_start}; -use crate::{arch, cpu::CpuId, trap::DisabledLocalIrqGuard}; +use crate::{arch, cpu::CpuId, trap::irq::DisabledLocalIrqGuard}; /// Defines a statically-allocated CPU-local variable. /// @@ -33,7 +33,7 @@ use crate::{arch, cpu::CpuId, trap::DisabledLocalIrqGuard}; /// let val_of_foo = ref_of_foo.load(Ordering::Relaxed); /// println!("FOO VAL: {}", val_of_foo); /// -/// let irq_guard = trap::disable_local(); +/// let irq_guard = trap::irq::disable_local(); /// let bar_guard = BAR.get_with(&irq_guard); /// let val_of_bar = bar_guard.get(); /// println!("BAR VAL: {}", val_of_bar); diff --git a/ostd/src/mm/tlb.rs b/ostd/src/mm/tlb.rs index 9cc99df68..bcf7d5874 100644 --- a/ostd/src/mm/tlb.rs +++ b/ostd/src/mm/tlb.rs @@ -77,7 +77,7 @@ impl<'a, G: PinCurrentCpu> TlbFlusher<'a, G> { /// function. But it may not be synchronous. Upon the return of this /// function, the TLB entries may not be coherent. pub fn dispatch_tlb_flush(&mut self) { - let irq_guard = crate::trap::disable_local(); + let irq_guard = crate::trap::irq::disable_local(); if self.ops_stack.is_empty() { return; diff --git a/ostd/src/panic.rs b/ostd/src/panic.rs index a25eec2d1..ea3b909cd 100644 --- a/ostd/src/panic.rs +++ b/ostd/src/panic.rs @@ -28,7 +28,7 @@ use unwinding::abi::{ #[linkage = "weak"] #[no_mangle] pub fn __ostd_panic_handler(info: &core::panic::PanicInfo) -> ! { - let _irq_guard = crate::trap::disable_local(); + let _irq_guard = crate::trap::irq::disable_local(); crate::cpu_local_cell! { static IN_PANIC: bool = false; diff --git a/ostd/src/smp.rs b/ostd/src/smp.rs index 81adfa624..3fbbcfe4e 100644 --- a/ostd/src/smp.rs +++ b/ostd/src/smp.rs @@ -14,7 +14,7 @@ use crate::{ cpu::{CpuSet, PinCurrentCpu}, cpu_local, sync::SpinLock, - trap::{self, IrqLine, TrapFrame}, + trap::{self, irq::IrqLine, TrapFrame}, }; /// Executes a function on other processors. @@ -32,7 +32,7 @@ use crate::{ /// The function `f` will be executed asynchronously on the target processors. /// However if called on the current processor, it will be synchronous. pub fn inter_processor_call(targets: &CpuSet, f: fn()) { - let irq_guard = trap::disable_local(); + let irq_guard = trap::irq::disable_local(); let this_cpu_id = irq_guard.current_cpu(); let ipi_data = IPI_GLOBAL_DATA.get().unwrap(); diff --git a/ostd/src/sync/guard.rs b/ostd/src/sync/guard.rs index ee3a3fbd6..5db5dd4da 100644 --- a/ostd/src/sync/guard.rs +++ b/ostd/src/sync/guard.rs @@ -2,7 +2,7 @@ use crate::{ task::{atomic_mode::AsAtomicModeGuard, disable_preempt, DisabledPreemptGuard}, - trap::{disable_local, DisabledLocalIrqGuard}, + trap::irq::{disable_local, DisabledLocalIrqGuard}, }; /// A guardian that denotes the guard behavior for holding a spin-based lock. diff --git a/ostd/src/task/kernel_stack.rs b/ostd/src/task/kernel_stack.rs index 0d648e6dd..4f1622655 100644 --- a/ostd/src/task/kernel_stack.rs +++ b/ostd/src/task/kernel_stack.rs @@ -12,7 +12,7 @@ use crate::{ FrameAllocOptions, PAGE_SIZE, }, prelude::*, - trap::DisabledLocalIrqGuard, + trap::irq::DisabledLocalIrqGuard, }; /// The kernel stack size of a task, specified in pages. diff --git a/ostd/src/task/processor.rs b/ostd/src/task/processor.rs index c74e066d6..329e5d3e3 100644 --- a/ostd/src/task/processor.rs +++ b/ostd/src/task/processor.rs @@ -4,7 +4,7 @@ use alloc::sync::Arc; use core::{ptr::NonNull, sync::atomic::Ordering}; use super::{context_switch, Task, TaskContext, POST_SCHEDULE_HANDLER}; -use crate::{cpu_local_cell, trap::DisabledLocalIrqGuard}; +use crate::{cpu_local_cell, trap::irq::DisabledLocalIrqGuard}; cpu_local_cell! { /// The `Arc` (casted by [`Arc::into_raw`]) that is the current task. @@ -43,7 +43,7 @@ pub(super) fn switch_to_task(next_task: Arc) { crate::sync::finish_grace_period(); } - let irq_guard = crate::trap::disable_local(); + let irq_guard = crate::trap::irq::disable_local(); let current_task_ptr = CURRENT_TASK_PTR.load(); let current_task_ctx_ptr = if !current_task_ptr.is_null() { diff --git a/ostd/src/timer/mod.rs b/ostd/src/timer/mod.rs index 92cd0859f..02056fa4d 100644 --- a/ostd/src/timer/mod.rs +++ b/ostd/src/timer/mod.rs @@ -22,7 +22,7 @@ pub fn register_callback(func: F) where F: Fn() + Sync + Send + 'static, { - let irq_guard = trap::disable_local(); + let irq_guard = trap::irq::disable_local(); INTERRUPT_CALLBACKS .get_with(&irq_guard) .borrow_mut() diff --git a/ostd/src/trap/handler.rs b/ostd/src/trap/handler.rs index f9fdd98f8..851df06a4 100644 --- a/ostd/src/trap/handler.rs +++ b/ostd/src/trap/handler.rs @@ -2,7 +2,7 @@ use spin::Once; -use super::{disable_local, irq::process_top_half, DisabledLocalIrqGuard}; +use super::irq::{disable_local, process_top_half, DisabledLocalIrqGuard}; use crate::{cpu_local_cell, task::disable_preempt, trap::TrapFrame}; static BOTTOM_HALF_HANDLER: Once DisabledLocalIrqGuard> = Once::new(); diff --git a/ostd/src/trap/irq.rs b/ostd/src/trap/irq.rs index a60fd3bbe..33423d669 100644 --- a/ostd/src/trap/irq.rs +++ b/ostd/src/trap/irq.rs @@ -1,5 +1,7 @@ // SPDX-License-Identifier: MPL-2.0 +//! IRQ line and IRQ guards. + use core::{fmt::Debug, ops::Deref}; use id_alloc::IdAlloc; @@ -141,6 +143,7 @@ fn get_or_init_allocator() -> &'static SpinLock { /// A handle for an allocated IRQ line. /// /// When the handle is dropped, the IRQ line will be released automatically. +#[must_use] #[derive(Debug)] struct InnerHandle { index: u8, @@ -204,10 +207,10 @@ pub(super) fn process_top_half(trap_frame: &TrapFrame, irq_num: usize) { /// # Example /// /// ```rust -/// use ostd::irq; +/// use ostd::trap; /// /// { -/// let _ = irq::disable_local(); +/// let _ = trap::irq::disable_local(); /// todo!("do something when irqs are disabled"); /// } /// ``` diff --git a/ostd/src/trap/mod.rs b/ostd/src/trap/mod.rs index 763be6f3a..921836068 100644 --- a/ostd/src/trap/mod.rs +++ b/ostd/src/trap/mod.rs @@ -3,10 +3,9 @@ //! Handles trap across kernel and user space. mod handler; -mod irq; +pub mod irq; +pub(crate) use handler::call_irq_callback_functions; pub use handler::{in_interrupt_context, register_bottom_half_handler}; -pub(crate) use self::handler::call_irq_callback_functions; -pub use self::irq::{disable_local, DisabledLocalIrqGuard, IrqCallbackFunction, IrqLine}; pub use crate::arch::trap::TrapFrame;