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Fix lint errors

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This commit is contained in:
Fabing Li
2025-02-27 03:09:05 +00:00
committed by Tate, Hongliang Tian
parent 82a2c4cdec
commit cbb4b4e631
24 changed files with 72 additions and 72 deletions
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18
ostd/src/arch/riscv/mm/mod.rs
View File

@ -150,15 +150,15 @@ impl PageTableEntryTrait for PageTableEntry {
}
fn prop(&self) -> PageProperty {
let flags = parse_flags!(self.0, PageTableFlags::READABLE, PageFlags::R)
| parse_flags!(self.0, PageTableFlags::WRITABLE, PageFlags::W)
| parse_flags!(self.0, PageTableFlags::EXECUTABLE, PageFlags::X)
| parse_flags!(self.0, PageTableFlags::ACCESSED, PageFlags::ACCESSED)
| parse_flags!(self.0, PageTableFlags::DIRTY, PageFlags::DIRTY)
| parse_flags!(self.0, PageTableFlags::RSV1, PageFlags::AVAIL1)
| parse_flags!(self.0, PageTableFlags::RSV2, PageFlags::AVAIL2);
let priv_flags = parse_flags!(self.0, PageTableFlags::USER, PrivFlags::USER)
| parse_flags!(self.0, PageTableFlags::GLOBAL, PrivFlags::GLOBAL);
let flags = (parse_flags!(self.0, PageTableFlags::READABLE, PageFlags::R))
| (parse_flags!(self.0, PageTableFlags::WRITABLE, PageFlags::W))
| (parse_flags!(self.0, PageTableFlags::EXECUTABLE, PageFlags::X))
| (parse_flags!(self.0, PageTableFlags::ACCESSED, PageFlags::ACCESSED))
| (parse_flags!(self.0, PageTableFlags::DIRTY, PageFlags::DIRTY))
| (parse_flags!(self.0, PageTableFlags::RSV1, PageFlags::AVAIL1))
| (parse_flags!(self.0, PageTableFlags::RSV2, PageFlags::AVAIL2));
let priv_flags = (parse_flags!(self.0, PageTableFlags::USER, PrivFlags::USER))
| (parse_flags!(self.0, PageTableFlags::GLOBAL, PrivFlags::GLOBAL));
let cache = if self.0 & PageTableFlags::PBMT_IO.bits() != 0 {
CachePolicy::Uncacheable

2
ostd/src/arch/x86/boot/multiboot/mod.rs
View File

@ -112,7 +112,7 @@ fn parse_memory_regions(mb1_info: &MultibootLegacyInfo) -> MemoryRegionArray {
regions
.push(MemoryRegion::new(
fb.address,
(fb.width * fb.height * fb.bpp + 7) / 8, // round up when divide with 8 (bits/Byte)
(fb.width * fb.height * fb.bpp).div_ceil(8), // round up when divide with 8 (bits/Byte)
MemoryRegionType::Framebuffer,
))
.unwrap();

2
ostd/src/arch/x86/boot/multiboot2/mod.rs
View File

@ -116,7 +116,7 @@ fn parse_memory_regions() -> MemoryRegionArray {
regions
.push(MemoryRegion::new(
fb.address,
(fb.width * fb.height * fb.bpp + 7) / 8, // round up when divide with 8 (bits/Byte)
(fb.width * fb.height * fb.bpp).div_ceil(8), // round up when divide with 8 (bits/Byte)
MemoryRegionType::Framebuffer,
))
.unwrap();

2
ostd/src/arch/x86/iommu/interrupt_remapping/table.rs
View File

@ -159,7 +159,7 @@ impl IrtEntry {
/// Enables this entry with no validation,
/// DST = 0, IM = 0, DLM = 0, TM = 0, RH = 0, DM = 0, FPD = 1, P = 1
pub fn enable_default(&mut self, vector: u32) {
self.0 = 0b11 | (vector as u128) << 16;
self.0 = 0b11 | ((vector as u128) << 16);
}
pub fn source_validation_type(&self) -> SourceValidationType {

14
ostd/src/arch/x86/kernel/apic/mod.rs
View File

@ -183,12 +183,12 @@ impl Icr {
ApicId::X2Apic(d) => (d as u64) << 32,
};
Icr(dest
| (destination_shorthand as u64) << 18
| (trigger_mode as u64) << 15
| (level as u64) << 14
| (delivery_status as u64) << 12
| (destination_mode as u64) << 11
| (delivery_mode as u64) << 8
| ((destination_shorthand as u64) << 18)
| ((trigger_mode as u64) << 15)
| ((level as u64) << 14)
| ((delivery_status as u64) << 12)
| ((destination_mode as u64) << 11)
| ((delivery_mode as u64) << 8)
| (vector as u64))
}
@ -219,7 +219,7 @@ impl ApicId {
/// Logical x2APIC ID = [(x2APIC ID[19:4] << 16) | (1 << x2APIC ID[3:0])]
#[expect(unused)]
pub fn x2apic_logical_id(&self) -> u32 {
self.x2apic_logical_cluster_id() << 16 | 1 << self.x2apic_logical_field_id()
(self.x2apic_logical_cluster_id() << 16) | (1 << self.x2apic_logical_field_id())
}
/// Returns the logical x2apic cluster ID.

4
ostd/src/arch/x86/kernel/apic/x2apic.rs
View File

@ -46,7 +46,7 @@ impl X2Apic {
}
// Set SVR, Enable APIC and set Spurious Vector to 15 (Reserved irq number)
let svr: u64 = 1 << 8 | 15;
let svr: u64 = (1 << 8) | 15;
wrmsr(IA32_X2APIC_SIVR, svr);
}
}
@ -73,7 +73,7 @@ impl super::Apic for X2Apic {
wrmsr(IA32_X2APIC_ICR, icr.0);
loop {
let icr = rdmsr(IA32_X2APIC_ICR);
if (icr >> 12 & 0x1) == 0 {
if ((icr >> 12) & 0x1) == 0 {
break;
}
if rdmsr(IA32_X2APIC_ESR) > 0 {

4
ostd/src/arch/x86/kernel/apic/xapic.rs
View File

@ -50,7 +50,7 @@ impl XApic {
set_apic_base_address(get_apic_base_address());
// Set SVR, Enable APIC and set Spurious Vector to 15 (Reserved irq number)
let svr: u32 = 1 << 8 | 15;
let svr: u32 = (1 << 8) | 15;
self.write(xapic::XAPIC_SVR, svr);
}
@ -83,7 +83,7 @@ impl super::Apic for XApic {
self.write(xapic::XAPIC_ICR0, icr.lower());
loop {
let icr = self.read(xapic::XAPIC_ICR0);
if (icr >> 12 & 0x1) == 0 {
if ((icr >> 12) & 0x1) == 0 {
break;
}
if self.read(xapic::XAPIC_ESR) > 0 {

48
ostd/src/arch/x86/mm/mod.rs
View File

@ -198,18 +198,18 @@ impl PageTableEntryTrait for PageTableEntry {
}
fn prop(&self) -> PageProperty {
let flags = parse_flags!(self.0, PageTableFlags::PRESENT, PageFlags::R)
| parse_flags!(self.0, PageTableFlags::WRITABLE, PageFlags::W)
| parse_flags!(!self.0, PageTableFlags::NO_EXECUTE, PageFlags::X)
| parse_flags!(self.0, PageTableFlags::ACCESSED, PageFlags::ACCESSED)
| parse_flags!(self.0, PageTableFlags::DIRTY, PageFlags::DIRTY)
| parse_flags!(self.0, PageTableFlags::HIGH_IGN1, PageFlags::AVAIL1)
| parse_flags!(self.0, PageTableFlags::HIGH_IGN2, PageFlags::AVAIL2);
let priv_flags = parse_flags!(self.0, PageTableFlags::USER, PrivFlags::USER)
| parse_flags!(self.0, PageTableFlags::GLOBAL, PrivFlags::GLOBAL);
let flags = (parse_flags!(self.0, PageTableFlags::PRESENT, PageFlags::R))
| (parse_flags!(self.0, PageTableFlags::WRITABLE, PageFlags::W))
| (parse_flags!(!self.0, PageTableFlags::NO_EXECUTE, PageFlags::X))
| (parse_flags!(self.0, PageTableFlags::ACCESSED, PageFlags::ACCESSED))
| (parse_flags!(self.0, PageTableFlags::DIRTY, PageFlags::DIRTY))
| (parse_flags!(self.0, PageTableFlags::HIGH_IGN1, PageFlags::AVAIL1))
| (parse_flags!(self.0, PageTableFlags::HIGH_IGN2, PageFlags::AVAIL2));
let priv_flags = (parse_flags!(self.0, PageTableFlags::USER, PrivFlags::USER))
| (parse_flags!(self.0, PageTableFlags::GLOBAL, PrivFlags::GLOBAL));
#[cfg(feature = "cvm_guest")]
let priv_flags =
priv_flags | parse_flags!(self.0, PageTableFlags::SHARED, PrivFlags::SHARED);
priv_flags | (parse_flags!(self.0, PageTableFlags::SHARED, PrivFlags::SHARED));
let cache = if self.0 & PageTableFlags::NO_CACHE.bits() != 0 {
CachePolicy::Uncacheable
} else if self.0 & PageTableFlags::WRITE_THROUGH.bits() != 0 {
@ -229,35 +229,35 @@ impl PageTableEntryTrait for PageTableEntry {
return;
}
let mut flags = PageTableFlags::empty().bits();
flags |= parse_flags!(prop.flags.bits(), PageFlags::R, PageTableFlags::PRESENT)
| parse_flags!(prop.flags.bits(), PageFlags::W, PageTableFlags::WRITABLE)
| parse_flags!(!prop.flags.bits(), PageFlags::X, PageTableFlags::NO_EXECUTE)
| parse_flags!(
flags |= (parse_flags!(prop.flags.bits(), PageFlags::R, PageTableFlags::PRESENT))
| (parse_flags!(prop.flags.bits(), PageFlags::W, PageTableFlags::WRITABLE))
| (parse_flags!(!prop.flags.bits(), PageFlags::X, PageTableFlags::NO_EXECUTE))
| (parse_flags!(
prop.flags.bits(),
PageFlags::ACCESSED,
PageTableFlags::ACCESSED
)
| parse_flags!(prop.flags.bits(), PageFlags::DIRTY, PageTableFlags::DIRTY)
| parse_flags!(
))
| (parse_flags!(prop.flags.bits(), PageFlags::DIRTY, PageTableFlags::DIRTY))
| (parse_flags!(
prop.flags.bits(),
PageFlags::AVAIL1,
PageTableFlags::HIGH_IGN1
)
| parse_flags!(
))
| (parse_flags!(
prop.flags.bits(),
PageFlags::AVAIL2,
PageTableFlags::HIGH_IGN2
)
| parse_flags!(
))
| (parse_flags!(
prop.priv_flags.bits(),
PrivFlags::USER,
PageTableFlags::USER
)
| parse_flags!(
))
| (parse_flags!(
prop.priv_flags.bits(),
PrivFlags::GLOBAL,
PageTableFlags::GLOBAL
);
));
#[cfg(feature = "cvm_guest")]
{
flags |= parse_flags!(

2
ostd/src/arch/x86/timer/hpet.rs
View File

@ -31,7 +31,7 @@ const HPET_FREQ: usize = 1_000_000_000_000_000;
#[repr(C)]
struct HpetTimerRegister {
configuration_and_capabilities_register: u32,
timer_compartor_value_register: u32,
timer_comparator_value_register: u32,
fsb_interrupt_route_register: u32,
}

4
ostd/src/arch/x86/timer/pit.rs
View File

@ -168,8 +168,8 @@ pub(crate) fn init(operating_mode: OperatingMode) {
// Bit 0 is BCD/binary mode, which is always set to binary mode(value: 0)
MODE_COMMAND_PORT.write(
((operating_mode as u8) << 1)
| (AccessMode::LowAndHighByte as u8) << 4
| (Channel::Channel0 as u8) << 6,
| ((AccessMode::LowAndHighByte as u8) << 4)
| ((Channel::Channel0 as u8) << 6),
);
// Set timer frequency

4
ostd/src/bus/pci/device_info.rs
View File

@ -141,7 +141,7 @@ impl PciDeviceLocation {
let mask = (0xFF << dest) as u32;
self.write32(
offset & Self::BIT32_ALIGN_MASK,
((val as u32) << dest | (old & !mask)).to_le(),
(((val as u32) << dest) | (old & !mask)).to_le(),
);
}
@ -151,7 +151,7 @@ impl PciDeviceLocation {
let mask = (0xFFFF << dest) as u32;
self.write32(
offset & Self::BIT32_ALIGN_MASK,
((val as u32) << dest | (old & !mask)).to_le(),
(((val as u32) << dest) | (old & !mask)).to_le(),
);
}

2
ostd/src/logger.rs
View File

@ -90,7 +90,7 @@ fn get_log_level() -> Option<LevelFilter> {
let value = kcmdline
.split(' ')
.find(|arg| arg.starts_with("ostd.log_level="))
.map(|arg| arg.split('=').last().unwrap_or_default())?;
.map(|arg| arg.split('=').next_back().unwrap_or_default())?;
LevelFilter::from_str(value).ok()
}

2
ostd/src/mm/page_table/mod.rs
View File

@ -73,7 +73,7 @@ const fn nr_pte_index_bits<C: PagingConstsTrait>() -> usize {
/// The index of a VA's PTE in a page table node at the given level.
const fn pte_index<C: PagingConstsTrait>(va: Vaddr, level: PagingLevel) -> usize {
va >> (C::BASE_PAGE_SIZE.ilog2() as usize + nr_pte_index_bits::<C>() * (level as usize - 1))
(va >> (C::BASE_PAGE_SIZE.ilog2() as usize + nr_pte_index_bits::<C>() * (level as usize - 1)))
& (nr_subpage_per_huge::<C>() - 1)
}