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Enable IA32_EFER.NXE
earlier in AP
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parent
9915978d35
commit
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@ -8,15 +8,23 @@
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.section ".ap_boot", "awx"
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.section ".ap_boot", "awx"
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.align 4096
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.align 4096
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IA32_APIC_BASE = 0x1B
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IA32_APIC_BASE_MSR = 0x1B
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IA32_X2APIC_APICID = 0x802
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IA32_X2APIC_APICID_MSR = 0x802
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MMIO_XAPIC_APICID = 0xFEE00020
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IA32_EFER_MSR = 0xC0000080
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XAPIC_APICID_MMIO_ADDR = 0xFEE00020
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.macro setup_64bit_gdt_and_page_table eax
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.macro setup_64bit_gdt_and_page_table eax
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// Use the 64-bit GDT.
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// Use the 64-bit GDT.
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.extern boot_gdtr
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.extern boot_gdtr
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lgdt [boot_gdtr]
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lgdt [boot_gdtr]
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// Set the NX bit support in the EFER MSR.
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mov ecx, IA32_EFER_MSR
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rdmsr
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or eax, 1 << 11 // support no-execute PTE flag
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wrmsr
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// Enable PAE and PGE.
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// Enable PAE and PGE.
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mov \eax, cr4
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mov \eax, cr4
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or \eax, 0xa0
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or \eax, 0xa0
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@ -25,6 +33,7 @@ MMIO_XAPIC_APICID = 0xFEE00020
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// Set the page table. The application processors use
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// Set the page table. The application processors use
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// the same page table as the bootstrap processor's
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// the same page table as the bootstrap processor's
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// boot phase page table.
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// boot phase page table.
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xor \eax, \eax // clear the upper 32 bits if \eax is 64-bit
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mov eax, __boot_page_table_pointer // 32-bit load
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mov eax, __boot_page_table_pointer // 32-bit load
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mov cr3, \eax
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mov cr3, \eax
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.endm
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.endm
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@ -106,11 +115,11 @@ ap_protect_entry:
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// Tell if it is xAPIC or x2APIC.
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// Tell if it is xAPIC or x2APIC.
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// IA32_APIC_BASE register:
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// IA32_APIC_BASE register:
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// bit 8: BSP—Processor is BSP
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// - bit 8: BSP—Processor is BSP
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// bit 10: EXTD—Enable x2APIC mode
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// - bit 10: EXTD—Enable x2APIC mode
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// bit 11: EN—xAPIC global enable/disable
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// - bit 11: EN—xAPIC global enable/disable
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// bit 12-35: APIC Base—Base physical address
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// - bit 12-35: APIC Base—Base physical address
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mov ecx, IA32_APIC_BASE
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mov ecx, IA32_APIC_BASE_MSR
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rdmsr
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rdmsr
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and eax, 0x400 // check EXTD bit
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and eax, 0x400 // check EXTD bit
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cmp eax, 0x400
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cmp eax, 0x400
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@ -119,14 +128,14 @@ ap_protect_entry:
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xapic_mode:
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xapic_mode:
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// In xAPIC mode, the local APIC ID is stored in
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// In xAPIC mode, the local APIC ID is stored in
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// the MMIO region.
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// the MMIO region.
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mov eax, [MMIO_XAPIC_APICID]
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mov eax, [XAPIC_APICID_MMIO_ADDR]
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shr eax, 24
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shr eax, 24
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jmp ap_protect
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jmp ap_protect
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x2apic_mode:
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x2apic_mode:
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// In x2APIC mode, the local APIC ID is stored in
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// In x2APIC mode, the local APIC ID is stored in
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// IA32_X2APIC_APICID MSR.
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// IA32_X2APIC_APICID MSR.
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mov ecx, IA32_X2APIC_APICID
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mov ecx, IA32_X2APIC_APICID_MSR
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rdmsr
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rdmsr
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jmp ap_protect
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jmp ap_protect
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@ -148,10 +157,10 @@ ap_protect:
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setup_64bit_gdt_and_page_table eax
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setup_64bit_gdt_and_page_table eax
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// Enable long mode.
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// Enable long mode.
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mov ecx, 0xc0000080
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mov ecx, IA32_EFER_MSR
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rdmsr // load EFER MSR
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rdmsr
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or eax, 1 << 8
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or eax, 1 << 8
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wrmsr // set long bit
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wrmsr
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// Enable paging.
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// Enable paging.
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mov eax, cr0
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mov eax, cr0
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