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Polish trap handler code

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Hsy-Intel 2023-09-27 15:09:32 +00:00 committed by Tate, Hongliang Tian
parent f2b2c20967
commit e8a2779bca
3 changed files with 32 additions and 41 deletions
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36
framework/jinux-frame/src/arch/x86/cpu.rs
View File

@ -44,51 +44,48 @@ pub struct TrapInformation {
}
#[cfg(feature = "intel_tdx")]
struct VeGeneralRegs<'a>(&'a mut GeneralRegs);
#[cfg(feature = "intel_tdx")]
impl TdxTrapFrame for VeGeneralRegs<'_> {
impl TdxTrapFrame for GeneralRegs {
fn rax(&self) -> usize {
self.0.rax
self.rax
}
fn set_rax(&mut self, rax: usize) {
self.0.rax = rax;
self.rax = rax;
}
fn rbx(&self) -> usize {
self.0.rbx
self.rbx
}
fn set_rbx(&mut self, rbx: usize) {
self.0.rbx = rbx;
self.rbx = rbx;
}
fn rcx(&self) -> usize {
self.0.rcx
self.rcx
}
fn set_rcx(&mut self, rcx: usize) {
self.0.rcx = rcx;
self.rcx = rcx;
}
fn rdx(&self) -> usize {
self.0.rdx
self.rdx
}
fn set_rdx(&mut self, rdx: usize) {
self.0.rdx = rdx;
self.rdx = rdx;
}
fn rsi(&self) -> usize {
self.0.rsi
self.rsi
}
fn set_rsi(&mut self, rsi: usize) {
self.0.rsi = rsi;
self.rsi = rsi;
}
fn rdi(&self) -> usize {
self.0.rdi
self.rdi
}
fn set_rdi(&mut self, rdi: usize) {
self.0.rdi = rdi;
self.rdi = rdi;
}
fn rip(&self) -> usize {
self.0.rip
self.rip
}
fn set_rip(&mut self, rip: usize) {
self.0.rip = rip;
self.rip = rip;
}
}
@ -130,8 +127,7 @@ impl UserContextApiInternal for UserContext {
if *exception == VIRTUALIZATION_EXCEPTION {
let ve_info =
tdcall::get_veinfo().expect("#VE handler: fail to get VE info\n");
let mut ve_f = VeGeneralRegs(self.general_regs_mut());
handle_virtual_exception(&mut ve_f, &ve_info);
handle_virtual_exception(self.general_regs_mut(), &ve_info);
continue;
}
if exception.typ == CpuExceptionType::FaultOrTrap

1
framework/jinux-frame/src/arch/x86/tdx_guest.rs
View File

@ -3,7 +3,6 @@ use tdx_guest::{
tdvmcall::{cpuid, hlt, rdmsr, wrmsr, IoSize},
{serial_println, tdcall, tdvmcall, TdxVirtualExceptionType},
};
use trapframe::{GeneralRegs, TrapFrame};
pub trait TdxTrapFrame {
fn rax(&self) -> usize;

36
framework/jinux-frame/src/trap/handler.rs
View File

@ -7,51 +7,48 @@ use tdx_guest::tdcall;
use trapframe::TrapFrame;
#[cfg(feature = "intel_tdx")]
struct VeTrapFrame<'a>(&'a mut TrapFrame);
#[cfg(feature = "intel_tdx")]
impl TdxTrapFrame for VeTrapFrame<'_> {
impl TdxTrapFrame for TrapFrame {
fn rax(&self) -> usize {
self.0.rax
self.rax
}
fn set_rax(&mut self, rax: usize) {
self.0.rax = rax;
self.rax = rax;
}
fn rbx(&self) -> usize {
self.0.rbx
self.rbx
}
fn set_rbx(&mut self, rbx: usize) {
self.0.rbx = rbx;
self.rbx = rbx;
}
fn rcx(&self) -> usize {
self.0.rcx
self.rcx
}
fn set_rcx(&mut self, rcx: usize) {
self.0.rcx = rcx;
self.rcx = rcx;
}
fn rdx(&self) -> usize {
self.0.rdx
self.rdx
}
fn set_rdx(&mut self, rdx: usize) {
self.0.rdx = rdx;
self.rdx = rdx;
}
fn rsi(&self) -> usize {
self.0.rsi
self.rsi
}
fn set_rsi(&mut self, rsi: usize) {
self.0.rsi = rsi;
self.rsi = rsi;
}
fn rdi(&self) -> usize {
self.0.rdi
self.rdi
}
fn set_rdi(&mut self, rdi: usize) {
self.0.rdi = rdi;
self.rdi = rdi;
}
fn rip(&self) -> usize {
self.0.rip
self.rip
}
fn set_rip(&mut self, rip: usize) {
self.0.rip = rip;
self.rip = rip;
}
}
@ -62,8 +59,7 @@ extern "sysv64" fn trap_handler(f: &mut TrapFrame) {
#[cfg(feature = "intel_tdx")]
if f.trap_num as u16 == 20 {
let ve_info = tdcall::get_veinfo().expect("#VE handler: fail to get VE info\n");
let mut ve_f = VeTrapFrame(f);
handle_virtual_exception(&mut ve_f, &ve_info);
handle_virtual_exception(f, &ve_info);
return;
}
panic!("cannot handle kernel cpu fault now, information:{:#x?}", f);