Avoid some #![expect(lint)]

ostd/src/arch/x86/iommu/fault.rs

@@ -1,8 +1,5 @@
 // SPDX-License-Identifier: MPL-2.0
 
-#![expect(dead_code)]
-#![expect(unused_variables)]
-
 use alloc::vec::Vec;
 use core::{fmt::Debug, ptr::NonNull};
 
@@ -21,13 +18,13 @@ use crate::trap::{IrqLine, TrapFrame};
 pub struct FaultEventRegisters {
     status: VolatileRef<'static, u32, ReadOnly>,
     /// bit31: Interrupt Mask; bit30: Interrupt Pending.
-    control: VolatileRef<'static, u32, ReadWrite>,
+    _control: VolatileRef<'static, u32, ReadWrite>,
-    data: VolatileRef<'static, u32, ReadWrite>,
+    _data: VolatileRef<'static, u32, ReadWrite>,
-    address: VolatileRef<'static, u32, ReadWrite>,
+    _address: VolatileRef<'static, u32, ReadWrite>,
-    upper_address: VolatileRef<'static, u32, ReadWrite>,
+    _upper_address: VolatileRef<'static, u32, ReadWrite>,
     recordings: Vec<VolatileRef<'static, u128, ReadOnly>>,
 
-    fault_irq: IrqLine,
+    _fault_irq: IrqLine,
 }
 
 impl FaultEventRegisters {
@@ -72,10 +69,7 @@ impl FaultEventRegisters {
             // value.
             recordings.push(unsafe {
                 VolatileRef::new_read_only(
-                    base_register_vaddr
+                    base_register_vaddr.add(offset).add(i * 16).cast::<u128>(),
-                        .add(offset)
-                        .add(i * 16)
-                        .cast::<u128>(),
                 )
             })
         }
@@ -90,12 +84,12 @@ impl FaultEventRegisters {
 
         FaultEventRegisters {
             status,
-            control,
+            _control: control,
-            data,
+            _data: data,
-            address,
+            _address: address,
-            upper_address,
+            _upper_address: upper_address,
             recordings,
-            fault_irq,
+            _fault_irq: fault_irq,
         }
     }
 }
@@ -148,6 +142,7 @@ impl FaultRecording {
         ((self.0 & 0xFFFF_FFFF_FFFF_F000) >> 12) as u64
     }
 
+    #[expect(dead_code)]
     pub fn pasid_value(&self) -> u32 {
         // bit 123:104
         ((self.0 & 0x00FF_FFF0_0000_0000_0000_0000_0000_0000) >> 104) as u32
@@ -158,16 +153,19 @@ impl FaultRecording {
         ((self.0 & 0xF_0000_0000_0000_0000_0000_0000) >> 96) as u8
     }
 
+    #[expect(dead_code)]
     pub fn pasid_present(&self) -> bool {
         // bit 95
         (self.0 & 0x8000_0000_0000_0000_0000_0000) != 0
     }
 
+    #[expect(dead_code)]
     pub fn execute_permission_request(&self) -> bool {
         // bit 94
         (self.0 & 0x4000_0000_0000_0000_0000_0000) != 0
     }
 
+    #[expect(dead_code)]
     pub fn privilege_mode_request(&self) -> bool {
         // bit 93
         (self.0 & 0x2000_0000_0000_0000_0000_0000) != 0
@@ -235,7 +233,7 @@ pub(super) unsafe fn init(base_register_vaddr: NonNull<u8>) {
     FAULT_EVENT_REGS.call_once(|| FaultEventRegisters::new(base_register_vaddr));
 }
 
-fn iommu_page_fault_handler(frame: &TrapFrame) {
+fn iommu_page_fault_handler(_frame: &TrapFrame) {
     let fault_event = FAULT_EVENT_REGS.get().unwrap();
     let index = (fault_event.status().bits & FaultStatus::FRI.bits) >> 8;
     let recording = FaultRecording(fault_event.recordings[index as usize].as_ptr().read());

ostd/src/arch/x86/timer/hpet.rs

@@ -1,7 +1,5 @@
 // SPDX-License-Identifier: MPL-2.0
 
-#![expect(dead_code)]
-
 use alloc::vec::Vec;
 use core::ptr::NonNull;
 
@@ -17,13 +15,16 @@ use crate::{
     mm::paddr_to_vaddr,
     trap::IrqLine,
 };
+
 static HPET_INSTANCE: Once<Hpet> = Once::new();
 
 const OFFSET_ID_REGISTER: usize = 0x000;
 const OFFSET_CONFIGURATION_REGISTER: usize = 0x010;
 const OFFSET_INTERRUPT_STATUS_REGISTER: usize = 0x020;
+#[expect(dead_code)]
 const OFFSET_MAIN_COUNTER_VALUE_REGISTER: usize = 0x0F0;
 
+#[expect(dead_code)]
 const HPET_FREQ: usize = 1_000_000_000_000_000;
 
 #[derive(Debug)]
@@ -36,11 +37,11 @@ struct HpetTimerRegister {
 
 struct Hpet {
     information_register: VolatileRef<'static, u32, ReadOnly>,
-    general_configuration_register: VolatileRef<'static, u32, ReadWrite>,
+    _general_configuration_register: VolatileRef<'static, u32, ReadWrite>,
-    general_interrupt_status_register: VolatileRef<'static, u32, ReadWrite>,
+    _general_interrupt_status_register: VolatileRef<'static, u32, ReadWrite>,
 
-    timer_registers: Vec<VolatileRef<'static, HpetTimerRegister, ReadWrite>>,
+    _timer_registers: Vec<VolatileRef<'static, HpetTimerRegister, ReadWrite>>,
-    irq: IrqLine,
+    _irq: IrqLine,
 }
 
 impl Hpet {
@@ -98,35 +99,41 @@ impl Hpet {
 
         Hpet {
             information_register,
-            general_configuration_register,
+            _general_configuration_register: general_configuration_register,
-            general_interrupt_status_register,
+            _general_interrupt_status_register: general_interrupt_status_register,
-            timer_registers: comparators,
+            _timer_registers: comparators,
-            irq,
+            _irq: irq,
         }
     }
 
+    #[expect(dead_code)]
     pub fn hardware_rev(&self) -> u8 {
         (self.information_register.as_ptr().read() & 0xFF) as u8
     }
 
+    #[expect(dead_code)]
     pub fn num_comparators(&self) -> u8 {
         ((self.information_register.as_ptr().read() & 0x1F00) >> 8) as u8 + 1
     }
 
+    #[expect(dead_code)]
     pub fn main_counter_is_64bits(&self) -> bool {
         (self.information_register.as_ptr().read() & 0x2000) != 0
     }
 
+    #[expect(dead_code)]
     pub fn legacy_irq_capable(&self) -> bool {
         (self.information_register.as_ptr().read() & 0x8000) != 0
     }
 
+    #[expect(dead_code)]
     pub fn pci_vendor_id(&self) -> u16 {
         ((self.information_register.as_ptr().read() & 0xFFFF_0000) >> 16) as u16
     }
 }
 
 /// HPET init, need to init IOAPIC before init this function
+#[expect(dead_code)]
 pub fn init() -> Result<(), AcpiError> {
     let hpet_info = {
         let lock = ACPI_TABLES.get().unwrap().lock();