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Move tdx_guest::unprotect_gpa_range
into IoMem creation
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parent
04a8fccd2f
commit
ef898e572c
@ -99,21 +99,6 @@ impl CapabilityMsixData {
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// Set message address 0xFEE0_0000
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for i in 0..table_size {
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#[cfg(target_arch = "x86_64")]
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crate::arch::if_tdx_enabled!({
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// SAFETY:
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// This is safe because we are ensuring that the physical address of the MSI-X table is valid before this operation.
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// We are also ensuring that we are only unprotecting a single page.
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// The MSI-X table will not exceed one page size, because the size of an MSI-X entry is 16 bytes, and 256 entries are required to fill a page,
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// which is just equal to the number of all the interrupt numbers on the x86 platform.
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// It is better to add a judgment here in case the device deliberately uses so many interrupt numbers.
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// In addition, due to granularity, the minimum value that can be set here is only one page.
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// Therefore, we are not causing any undefined behavior or violating any of the requirements of the `unprotect_gpa_range` function.
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unsafe {
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crate::arch::tdx_guest::unprotect_gpa_range(table_bar.io_mem().paddr(), 1)
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.unwrap();
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}
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});
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// Set message address and disable this msix entry
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table_bar
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.io_mem()
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@ -90,6 +90,17 @@ impl IoMem {
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#[cfg(target_arch = "x86_64")]
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{
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crate::arch::if_tdx_enabled!({
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if first_page_start != range.start || last_page_end != range.end {
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panic!("Alignment check failed when TDX is enabled. Requested IoMem range: {:#x?}..{:#x?}", range.start, range.end);
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}
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let pages = (last_page_end - first_page_start) / PAGE_SIZE;
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// SAFETY:
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// This is safe because we are ensuring that the physical address must be in the I/O memory region, and only unprotecting this region.
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unsafe {
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crate::arch::tdx_guest::unprotect_gpa_range(first_page_start, pages).unwrap();
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}
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PrivilegedPageFlags::SHARED
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} else {
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PrivilegedPageFlags::empty()
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