diff --git a/ostd/src/arch/riscv/device/io_port.rs b/ostd/src/arch/riscv/device/io_port.rs index ee70bde77..f2bcbacc5 100644 --- a/ostd/src/arch/riscv/device/io_port.rs +++ b/ostd/src/arch/riscv/device/io_port.rs @@ -32,53 +32,3 @@ impl PortRead for u16 {} impl PortWrite for u16 {} impl PortRead for u32 {} impl PortWrite for u32 {} - -/// An I/O port, representing a specific address in the I/O address of x86. -/// -/// The following code shows and example to read and write u32 value to an I/O port: -/// -/// ```rust -/// static PORT: IoPort = unsafe { IoPort::new(0x12) }; -/// -/// fn port_value_increase(){ -/// PORT.write(PORT.read() + 1) -/// } -/// ``` -/// -pub struct IoPort { - port: u16, - value_marker: PhantomData, - access_marker: PhantomData, -} - -impl IoPort { - /// Create an I/O port. - /// - /// # Safety - /// - /// This function is marked unsafe as creating an I/O port is considered - /// a privileged operation. - pub const unsafe fn new(port: u16) -> Self { - Self { - port, - value_marker: PhantomData, - access_marker: PhantomData, - } - } -} - -impl IoPort { - /// Reads from the I/O port - #[inline] - pub fn read(&self) -> T { - unsafe { PortRead::read_from_port(self.port) } - } -} - -impl IoPort { - /// Writes to the I/O port - #[inline] - pub fn write(&self, value: T) { - unsafe { PortWrite::write_to_port(self.port, value) } - } -} diff --git a/ostd/src/arch/x86/device/cmos.rs b/ostd/src/arch/x86/device/cmos.rs index b7b1316d2..8b4d78f17 100644 --- a/ostd/src/arch/x86/device/cmos.rs +++ b/ostd/src/arch/x86/device/cmos.rs @@ -12,8 +12,7 @@ use acpi::fadt::Fadt; use x86_64::instructions::port::{ReadOnlyAccess, WriteOnlyAccess}; -use super::io_port::IoPort; -use crate::arch::x86::kernel::acpi::get_acpi_tables; +use crate::{arch::x86::kernel::acpi::get_acpi_tables, io::IoPort}; /// CMOS address I/O port pub static CMOS_ADDRESS: IoPort = unsafe { IoPort::new(0x70) }; diff --git a/ostd/src/arch/x86/device/io_port.rs b/ostd/src/arch/x86/device/io_port.rs index fda5a1016..9ebfcaa1f 100644 --- a/ostd/src/arch/x86/device/io_port.rs +++ b/ostd/src/arch/x86/device/io_port.rs @@ -2,8 +2,6 @@ //! I/O port access. -use core::marker::PhantomData; - pub use x86_64::{ instructions::port::{ PortReadAccess as IoPortReadAccess, PortWriteAccess as IoPortWriteAccess, ReadOnlyAccess, @@ -11,53 +9,3 @@ pub use x86_64::{ }, structures::port::{PortRead, PortWrite}, }; - -/// An I/O port, representing a specific address in the I/O address of x86. -/// -/// The following code shows and example to read and write u32 value to an I/O port: -/// -/// ```rust -/// static PORT: IoPort = unsafe { IoPort::new(0x12) }; -/// -/// fn port_value_increase(){ -/// PORT.write(PORT.read() + 1) -/// } -/// ``` -/// -pub struct IoPort { - port: u16, - value_marker: PhantomData, - access_marker: PhantomData, -} - -impl IoPort { - /// Creates an I/O port. - /// - /// # Safety - /// - /// This function is marked unsafe as creating an I/O port is considered - /// a privileged operation. - pub const unsafe fn new(port: u16) -> Self { - Self { - port, - value_marker: PhantomData, - access_marker: PhantomData, - } - } -} - -impl IoPort { - /// Reads from the I/O port - #[inline] - pub fn read(&self) -> T { - unsafe { PortRead::read_from_port(self.port) } - } -} - -impl IoPort { - /// Writes to the I/O port - #[inline] - pub fn write(&self, value: T) { - unsafe { PortWrite::write_to_port(self.port, value) } - } -} diff --git a/ostd/src/arch/x86/device/serial.rs b/ostd/src/arch/x86/device/serial.rs index 2fa15c723..0c7eadf49 100644 --- a/ostd/src/arch/x86/device/serial.rs +++ b/ostd/src/arch/x86/device/serial.rs @@ -4,8 +4,10 @@ #![expect(dead_code)] -use crate::arch::x86::device::io_port::{IoPort, ReadWriteAccess, WriteOnlyAccess}; - +use crate::{ + arch::x86::device::io_port::{ReadWriteAccess, WriteOnlyAccess}, + io::IoPort, +}; /// A serial port. /// /// Serial ports are a legacy communications port common on IBM-PC compatible computers. diff --git a/ostd/src/arch/x86/kernel/pic.rs b/ostd/src/arch/x86/kernel/pic.rs index 4a2804ef1..24cba4999 100644 --- a/ostd/src/arch/x86/kernel/pic.rs +++ b/ostd/src/arch/x86/kernel/pic.rs @@ -6,10 +6,7 @@ use core::sync::atomic::{AtomicBool, AtomicU8, Ordering::Relaxed}; use log::info; -use crate::{ - arch::x86::device::io_port::{IoPort, WriteOnlyAccess}, - trap::IrqLine, -}; +use crate::{arch::x86::device::io_port::WriteOnlyAccess, io::IoPort, trap::IrqLine}; static MASTER_CMD: IoPort = unsafe { IoPort::new(0x20) }; static MASTER_DATA: IoPort = unsafe { IoPort::new(0x21) }; diff --git a/ostd/src/arch/x86/pci.rs b/ostd/src/arch/x86/pci.rs index f54828d3c..3bad24392 100644 --- a/ostd/src/arch/x86/pci.rs +++ b/ostd/src/arch/x86/pci.rs @@ -2,8 +2,8 @@ //! PCI bus access -use super::device::io_port::{IoPort, ReadWriteAccess, WriteOnlyAccess}; -use crate::{bus::pci::PciDeviceLocation, prelude::*}; +use super::device::io_port::{ReadWriteAccess, WriteOnlyAccess}; +use crate::{bus::pci::PciDeviceLocation, io::IoPort, prelude::*}; static PCI_ADDRESS_PORT: IoPort = unsafe { IoPort::new(0x0CF8) }; static PCI_DATA_PORT: IoPort = unsafe { IoPort::new(0x0CFC) }; diff --git a/ostd/src/arch/x86/timer/pit.rs b/ostd/src/arch/x86/timer/pit.rs index 7db43e7ed..ad25848b4 100644 --- a/ostd/src/arch/x86/timer/pit.rs +++ b/ostd/src/arch/x86/timer/pit.rs @@ -10,11 +10,8 @@ //! use crate::{ - arch::{ - kernel::IO_APIC, - timer::TIMER_FREQ, - x86::device::io_port::{IoPort, WriteOnlyAccess}, - }, + arch::{kernel::IO_APIC, timer::TIMER_FREQ, x86::device::io_port::WriteOnlyAccess}, + io::IoPort, trap::IrqLine, }; diff --git a/ostd/src/io/io_port/mod.rs b/ostd/src/io/io_port/mod.rs new file mode 100644 index 000000000..39bdc415f --- /dev/null +++ b/ostd/src/io/io_port/mod.rs @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: MPL-2.0 + +//! I/O port and its allocator that allocates port I/O (PIO) to device drivers. + +use core::marker::PhantomData; + +use crate::arch::device::io_port::{IoPortReadAccess, IoPortWriteAccess, PortRead, PortWrite}; + +/// An I/O port, representing a specific address in the I/O address of x86. +/// +/// The following code shows and example to read and write u32 value to an I/O port: +/// +/// ```rust +/// static PORT: IoPort = unsafe { IoPort::new(0x12) }; +/// +/// fn port_value_increase(){ +/// PORT.write(PORT.read() + 1) +/// } +/// ``` +/// +pub struct IoPort { + port: u16, + value_marker: PhantomData, + access_marker: PhantomData, +} + +impl IoPort { + /// Create an I/O port. + /// + /// # Safety + /// + /// This function is marked unsafe as creating an I/O port is considered + /// a privileged operation. + pub const unsafe fn new(port: u16) -> Self { + Self { + port, + value_marker: PhantomData, + access_marker: PhantomData, + } + } +} + +impl IoPort { + /// Reads from the I/O port + #[inline] + pub fn read(&self) -> T { + unsafe { PortRead::read_from_port(self.port) } + } +} + +impl IoPort { + /// Writes to the I/O port + #[inline] + pub fn write(&self, value: T) { + unsafe { PortWrite::write_to_port(self.port, value) } + } +} diff --git a/ostd/src/io/mod.rs b/ostd/src/io/mod.rs index 908f7f8a0..12fd87d10 100644 --- a/ostd/src/io/mod.rs +++ b/ostd/src/io/mod.rs @@ -8,9 +8,10 @@ //! - `IoPort` for port I/O (PIO). mod io_mem; +mod io_port; -pub use self::io_mem::IoMem; pub(crate) use self::io_mem::IoMemAllocatorBuilder; +pub use self::{io_mem::IoMem, io_port::IoPort}; /// Initializes the static allocator based on builder. ///