11 Commits

Author	SHA1	Message	Date
Ruihan Li	35e0918bce	Don't race between enabling IRQs and halting CPU	2025-06-23 22:53:35 +08:00
Zejun Zhao	bd24ed9ba7	Support RISC-V ISA extension detection	2025-06-11 16:54:59 +08:00
Zejun Zhao	ffb4097436	Add RISC-V timer support	2025-05-29 19:51:02 +08:00
Zejun Zhao	3aa1079ca6	Clarify the usage of ostd::arch	2025-04-18 13:26:16 +08:00
Zejun Zhao	14b8c48859	Adjust RISC-V's implementation for recent changes	2025-04-18 13:26:16 +08:00
Ruihan Li	5651b93af0	Turn GS.base validity into a global invariant	2025-04-03 10:50:22 +08:00
Zhang Junyang	30ec0be210	Halt the idle CPUs	2025-03-21 21:19:50 +08:00
Zhang Junyang	f1c7564184	Move CPU context implementations to a specific module	2025-03-21 21:19:50 +08:00
Zhang Junyang	fc67adb1f0	Move arch/cpu/context files ... This commit can't compile, turn to the next one instead. But if melding this commit with the next one, Git cannot detect rename changes.	2025-03-21 21:19:50 +08:00
Qingsong Chen	5e35704e38	Support eagerly FPU state save/restore ... Co-authored-by: Shaowei Song <songshaowei.ssw@antgroup.com>	2024-11-29 21:53:14 +08:00
YanWQ-monad	4fa0e6334b	Add RISC-V base support	2024-09-30 10:02:08 +08:00