Zejun Zhao 14b8c48859 Adjust RISC-V's implementation for recent changes

2025-04-18 13:26:16 +08:00

..

arch

Adjust RISC-V's implementation for recent changes

2025-04-18 13:26:16 +08:00

boot

Fix safety reasoning about get_on_cpu

2025-04-03 10:50:22 +08:00

bus

Adjust RISC-V's implementation for recent changes

2025-04-18 13:26:16 +08:00

collections

Rename aster-frame to ostd

2024-06-27 15:45:49 +08:00

cpu

Remove unnecessary usage of cfg_if macro

2025-04-18 13:26:16 +08:00

io

Make IoPort x86-specific

2025-04-18 13:26:16 +08:00

mm

Adjust RISC-V's implementation for recent changes

2025-04-18 13:26:16 +08:00

sync

Add guard which disables bottom half

2025-04-15 14:54:51 +08:00

task

Adjust RISC-V's implementation for recent changes

2025-04-18 13:26:16 +08:00

timer

Extract shared code from timer

2024-09-30 10:02:08 +08:00

trap

Add guard which disables bottom half

2025-04-15 14:54:51 +08:00

util

Add support for Rcu to store an Either

2025-04-15 10:10:42 +08:00

console.rs

Adjust RISC-V's implementation for recent changes

2025-04-18 13:26:16 +08:00

error.rs

Refactor kernel virtual memory allocation for kernel stack and I/O memory

2024-10-21 09:53:05 +08:00

lib.rs

Make if_tdx_enabled macro x86-specific

2025-04-18 13:26:16 +08:00

logger.rs

Move the log lock to a better location

2025-04-16 21:59:24 +08:00

panic.rs

Remove the linkage feature usage for ostd::main

2024-10-20 13:24:58 +08:00

prelude.rs

Implement a new set of physical page APIs

2024-12-27 12:12:51 +08:00

smp.rs

Use CpuId with validity ensurance rather than u32

2024-10-26 22:06:41 +08:00

user.rs

Move CPU context implementations to a specific module

2025-03-21 21:19:50 +08:00