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https://github.com/asterinas/asterinas.git
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345 lines
10 KiB
Rust
345 lines
10 KiB
Rust
// SPDX-License-Identifier: MPL-2.0
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#![expect(dead_code)]
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use alloc::collections::BTreeMap;
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use core::mem::size_of;
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use log::trace;
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use ostd_pod::Pod;
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use super::second_stage::{DeviceMode, PageTableEntry, PagingConsts};
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use crate::{
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bus::pci::PciDeviceLocation,
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mm::{
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dma::Daddr,
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page_prop::{CachePolicy, PageProperty, PrivilegedPageFlags as PrivFlags},
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page_table::{PageTableError, PageTableItem},
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Frame, FrameAllocOptions, Paddr, PageFlags, PageTable, VmIo, PAGE_SIZE,
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},
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task::disable_preempt,
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};
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/// Bit 0 is `Present` bit, indicating whether this entry is present.
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/// Bit 63:12 is the context-table pointer pointing to this bus's context-table.
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#[derive(Pod, Clone, Copy)]
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#[repr(C)]
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pub struct RootEntry(u128);
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impl RootEntry {
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pub const fn is_present(&self) -> bool {
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// Bit 0
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(self.0 & 0b1) != 0
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}
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pub const fn addr(&self) -> u64 {
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(self.0 & 0xFFFF_FFFF_FFFF_F000) as u64
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}
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}
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pub struct RootTable {
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/// Total 256 bus, each entry is 128 bits.
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root_frame: Frame<()>,
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// TODO: Use radix tree instead.
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context_tables: BTreeMap<Paddr, ContextTable>,
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}
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#[derive(Debug)]
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pub enum ContextTableError {
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InvalidDeviceId,
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/// Error when modifying the page table
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ModificationError(PageTableError),
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}
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impl RootTable {
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pub fn root_paddr(&self) -> Paddr {
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self.root_frame.start_paddr()
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}
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pub(super) fn new() -> Self {
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Self {
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root_frame: FrameAllocOptions::new().alloc_frame().unwrap(),
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context_tables: BTreeMap::new(),
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}
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}
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/// Mapping device address to physical address.
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///
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/// # Safety
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///
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/// User must ensure the given paddr is a valid one.
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pub(super) unsafe fn map(
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&mut self,
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device: PciDeviceLocation,
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daddr: Daddr,
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paddr: Paddr,
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) -> Result<(), ContextTableError> {
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if device.device >= 32 || device.function >= 8 {
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return Err(ContextTableError::InvalidDeviceId);
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}
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let context_table = self.get_or_create_context_table(device);
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// SAFETY: The safety is upheld by the caller.
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unsafe { context_table.map(device, daddr, paddr)? };
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Ok(())
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}
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pub(super) fn unmap(
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&mut self,
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device: PciDeviceLocation,
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daddr: Daddr,
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) -> Result<(), ContextTableError> {
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if device.device >= 32 || device.function >= 8 {
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return Err(ContextTableError::InvalidDeviceId);
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}
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let context_table = self.get_or_create_context_table(device);
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context_table.unmap(device, daddr)?;
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Ok(())
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}
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/// Specifies the device page table instead of creating a page table if not exists.
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///
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/// This will be useful if we want all the devices to use the same page table.
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/// The original page table will be overwritten.
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pub(super) fn specify_device_page_table(
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&mut self,
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device_id: PciDeviceLocation,
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page_table: PageTable<DeviceMode, PageTableEntry, PagingConsts>,
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) {
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let context_table = self.get_or_create_context_table(device_id);
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let bus_entry = context_table
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.entries_frame
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.read_val::<ContextEntry>(
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(device_id.device as usize * 8 + device_id.function as usize)
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* size_of::<ContextEntry>(),
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)
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.unwrap();
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if bus_entry.is_present() {
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panic!("existing device page tables should not be overridden");
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}
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// Activate page table.
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let address = page_table.root_paddr();
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context_table.page_tables.insert(address, page_table);
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let entry = ContextEntry(address as u128 | 1 | 0x1_0000_0000_0000_0000);
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context_table
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.entries_frame
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.write_val::<ContextEntry>(
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(device_id.device as usize * 8 + device_id.function as usize)
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* size_of::<ContextEntry>(),
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&entry,
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)
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.unwrap();
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}
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fn get_or_create_context_table(&mut self, device_id: PciDeviceLocation) -> &mut ContextTable {
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let bus_entry = self
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.root_frame
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.read_val::<RootEntry>(device_id.bus as usize * size_of::<RootEntry>())
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.unwrap();
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if !bus_entry.is_present() {
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let table = ContextTable::new();
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let address = table.paddr();
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self.context_tables.insert(address, table);
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let entry = RootEntry(address as u128 | 1);
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self.root_frame
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.write_val::<RootEntry>(device_id.bus as usize * size_of::<RootEntry>(), &entry)
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.unwrap();
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self.context_tables.get_mut(&address).unwrap()
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} else {
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self.context_tables
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.get_mut(&(bus_entry.addr() as usize))
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.unwrap()
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}
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}
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}
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/// Context Entry in the Context Table, used in Intel iommu.
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///
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/// The format of context entry:
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/// ```
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/// 127--88: Reserved.
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/// 87---72: Domain Identifier.
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/// 71---71: Reserved.
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/// 70---67: Ignored.
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/// 66---64: Address Width.
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/// 63---12: Second Stage Page Translation Pointer.
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/// 11----4: Reserved.
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/// 3-----2: Translation Type.
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/// 1-----1: Fault Processing Disable.
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/// 0-----0: Present
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/// ```
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///
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#[derive(Pod, Clone, Copy)]
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#[repr(C)]
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pub struct ContextEntry(u128);
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impl ContextEntry {
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/// Identifier for the domain to which this context-entry maps. Hardware may use the domain
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/// identifier to tag its internal caches
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pub const fn domain_identifier(&self) -> u64 {
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// Bit 87-72
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((self.0 & 0xFF_FF00_0000_0000_0000_0000) >> 72) as u64
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}
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pub const fn address_width(&self) -> AddressWidth {
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// Bit 66-64
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let value = ((self.0 & 0x7_0000_0000_0000_0000) >> 64) as u64;
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match value {
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1 => AddressWidth::Level3PageTable,
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2 => AddressWidth::Level4PageTable,
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3 => AddressWidth::Level5PageTable,
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_ => AddressWidth::Reserved,
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}
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}
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/// Gets the second stage page translation pointer.
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///
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/// This function will not right shift the value after the `and` operation.
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pub const fn second_stage_pointer(&self) -> u64 {
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// Bit 63~12
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(self.0 & 0xFFFF_FFFF_FFFF_F000) as u64
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}
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/// This field is applicable only for requests-without-PASID, as hardware blocks all requests-with
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/// PASID in legacy mode before they can use context table
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pub const fn translation_type(&self) -> u64 {
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// Bit 3~2
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((self.0 & 0b1100) >> 2) as u64
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}
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/// Whether need to record/report qualified non-recoverable faults.
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pub const fn need_fault_process(&self) -> bool {
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// Bit 1
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(self.0 & 0b10) == 0
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}
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pub const fn is_present(&self) -> bool {
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// Bit 0
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(self.0 & 0b1) != 0
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}
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}
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#[derive(Debug)]
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pub enum AddressWidth {
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/// 000b, 100b~111b
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Reserved,
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/// 001b
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Level3PageTable,
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/// 010b
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Level4PageTable,
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/// 011b
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Level5PageTable,
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}
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pub struct ContextTable {
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/// Total 32 devices, each device has 8 functions.
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entries_frame: Frame<()>,
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page_tables: BTreeMap<Paddr, PageTable<DeviceMode, PageTableEntry, PagingConsts>>,
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}
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impl ContextTable {
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fn new() -> Self {
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Self {
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entries_frame: FrameAllocOptions::new().alloc_frame().unwrap(),
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page_tables: BTreeMap::new(),
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}
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}
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fn paddr(&self) -> Paddr {
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self.entries_frame.start_paddr()
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}
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fn get_or_create_page_table(
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&mut self,
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device: PciDeviceLocation,
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) -> &mut PageTable<DeviceMode, PageTableEntry, PagingConsts> {
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let bus_entry = self
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.entries_frame
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.read_val::<ContextEntry>(
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(device.device as usize * 8 + device.function as usize) * size_of::<ContextEntry>(),
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)
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.unwrap();
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if !bus_entry.is_present() {
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let table = PageTable::<DeviceMode, PageTableEntry, PagingConsts>::empty();
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let address = table.root_paddr();
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self.page_tables.insert(address, table);
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let entry = ContextEntry(address as u128 | 3 | 0x1_0000_0000_0000_0000);
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self.entries_frame
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.write_val::<ContextEntry>(
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(device.device as usize * 8 + device.function as usize)
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* size_of::<ContextEntry>(),
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&entry,
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)
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.unwrap();
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self.page_tables.get_mut(&address).unwrap()
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} else {
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self.page_tables
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.get_mut(&(bus_entry.second_stage_pointer() as usize))
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.unwrap()
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}
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}
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/// # Safety
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///
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/// User must ensure that the given physical address is valid.
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unsafe fn map(
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&mut self,
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device: PciDeviceLocation,
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daddr: Daddr,
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paddr: Paddr,
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) -> Result<(), ContextTableError> {
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if device.device >= 32 || device.function >= 8 {
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return Err(ContextTableError::InvalidDeviceId);
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}
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trace!(
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"Mapping Daddr: {:x?} to Paddr: {:x?} for device: {:x?}",
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daddr,
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paddr,
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device
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);
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let from = daddr..daddr + PAGE_SIZE;
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let to = paddr..paddr + PAGE_SIZE;
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let prop = PageProperty {
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flags: PageFlags::RW,
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cache: CachePolicy::Uncacheable,
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priv_flags: PrivFlags::empty(),
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};
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let pt = self.get_or_create_page_table(device);
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// SAFETY: The safety is upheld by the caller.
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unsafe { pt.map(&from, &to, prop).unwrap() };
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Ok(())
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}
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fn unmap(&mut self, device: PciDeviceLocation, daddr: Daddr) -> Result<(), ContextTableError> {
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if device.device >= 32 || device.function >= 8 {
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return Err(ContextTableError::InvalidDeviceId);
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}
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trace!("Unmapping Daddr: {:x?} for device: {:x?}", daddr, device);
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let pt = self.get_or_create_page_table(device);
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let preempt_guard = disable_preempt();
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let mut cursor = pt
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.cursor_mut(&preempt_guard, &(daddr..daddr + PAGE_SIZE))
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.unwrap();
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// SAFETY: This unmaps a page from the context table, which is always safe.
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let item = unsafe { cursor.take_next(PAGE_SIZE) };
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debug_assert!(matches!(item, PageTableItem::MappedUntracked { .. }));
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Ok(())
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}
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}
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