Ruihan Li c17a3eaa0b Revise safety comments in single_instr.rs

2025-04-03 10:50:22 +08:00

..

arch

Revise safety comments in single_instr.rs

2025-04-03 10:50:22 +08:00

boot

Turn GS.base validity into a global invariant

2025-04-03 10:50:22 +08:00

bus

Refactor PCI access in OSTD

2025-03-29 09:16:40 +08:00

collections

Rename aster-frame to ostd

2024-06-27 15:45:49 +08:00

cpu

Revise safety comments in single_instr.rs

2025-04-03 10:50:22 +08:00

io

Fix TLB coherence of KVirtArea a bit

2025-03-25 17:35:54 +08:00

mm

Ignore unusable regions for max_paddr

2025-04-02 11:50:33 +08:00

sync

Allow RCU to read with an atomic-mode guard

2025-03-25 22:34:26 +08:00

task

Enforce a task not switched to multiple CPUs

2025-04-02 20:51:42 +08:00

timer

Extract shared code from timer

2024-09-30 10:02:08 +08:00

trap

Introduce the semantics of the atomic-mode guard

2025-03-25 22:34:26 +08:00

util

Refactor and rename VirtAddrAllocator to RangeAllocator

2025-03-22 17:38:30 +08:00

console.rs

Don't force every printer to use if_tdx_enabled

2025-03-22 10:16:43 +08:00

error.rs

Refactor kernel virtual memory allocation for kernel stack and I/O memory

2024-10-21 09:53:05 +08:00

lib.rs

Turn GS.base validity into a global invariant

2025-04-03 10:50:22 +08:00

logger.rs

Fix lint errors

2025-02-27 11:36:41 +08:00

panic.rs

Remove the linkage feature usage for ostd::main

2024-10-20 13:24:58 +08:00

prelude.rs

Implement a new set of physical page APIs

2024-12-27 12:12:51 +08:00

smp.rs

Use CpuId with validity ensurance rather than u32

2024-10-26 22:06:41 +08:00

user.rs

Move CPU context implementations to a specific module

2025-03-21 21:19:50 +08:00