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https://github.com/DragonOS-Community/DragonOS.git
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190 lines
7.7 KiB
C
190 lines
7.7 KiB
C
#pragma once
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#include <driver/usb/usb.h>
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#include <driver/pci/pci.h>
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#define XHCI_MAX_HOST_CONTROLLERS 8
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#define XHCI_MAX_ROOT_HUB_PORTS 128
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// xhci Capability Registers offset
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#define XHCI_CAPS_CAPLENGTH 0x00 // Cap 寄存器组的长度
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#define XHCI_CAPS_RESERVED 0x01
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#define XHCI_CAPS_HCIVERSION 0x02 // 接口版本号
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#define XHCI_CAPS_HCSPARAMS1 0x04
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#define XHCI_CAPS_HCSPARAMS2 0x08
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#define XHCI_CAPS_HCSPARAMS3 0x0c
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#define XHCI_CAPS_HCCPARAMS1 0x10 // capability params 1
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#define XHCI_CAPS_DBOFF 0x14 // Doorbell offset
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#define XHCI_CAPS_RTSOFF 0x18 // Runtime register space offset
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#define XHCI_CAPS_HCCPARAMS2 0x1c // capability params 2
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struct xhci_caps_HCSPARAMS1_reg_t
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{
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unsigned max_slots : 8; // 最大插槽数
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unsigned max_intrs : 11; // 最大中断数
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unsigned reserved : 5;
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unsigned max_ports : 8; // 最大端口数
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} __attribute__((packed));
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struct xhci_caps_HCSPARAMS2_reg_t
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{
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unsigned ist : 4; // 同步调度阈值
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unsigned ERST_Max : 4; // Event Ring Segment Table Max
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unsigned Reserved : 13;
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unsigned max_scratchpad_buf_HI5 : 5; // 草稿行buffer地址（高5bit）
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unsigned spr : 1; // scratchpad restore
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unsigned max_scratchpad_buf_LO5 : 5; // 草稿行buffer地址（低5bit）
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} __attribute__((packed));
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struct xhci_caps_HCSPARAMS3_reg_t
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{
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uint8_t u1_device_exit_latency; // 0~10ms
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uint8_t Reserved;
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uint16_t u2_device_exit_latency; // 0~2047ms
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} __attribute__((packed));
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struct xhci_caps_HCCPARAMS1_reg_t
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{
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unsigned int ac64 : 1; // 64-bit addressing capability
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unsigned int bnc : 1; // bw negotiation capability
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unsigned int csz : 1; // context size
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unsigned int ppc : 1; // 端口电源控制
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unsigned int pind : 1; // port indicators
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unsigned int lhrc : 1; // Light HC reset capability
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unsigned int ltc : 1; // latency tolerance messaging capability
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unsigned int nss : 1; // no secondary SID support
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unsigned int pae : 1; // parse all event data
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unsigned int spc : 1; // Stopped - Short packet capability
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unsigned int sec : 1; // Stopped EDTLA capability
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unsigned int cfc : 1; // Continuous Frame ID capability
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unsigned int MaxPSASize : 4; // Max Primary Stream Array Size
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uint16_t xECP; // xhci extended capabilities pointer
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} __attribute__((packed));
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struct xhci_caps_HCCPARAMS2_reg_t
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{
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unsigned u3c : 1; // U3 Entry Capability
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unsigned cmc : 1; // ConfigEP command Max exit latency too large
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unsigned fsc : 1; // Force Save Context Capability
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unsigned ctc : 1; // Compliance Transition Capability
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unsigned lec : 1; // large ESIT payload capability
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unsigned cic : 1; // configuration information capability
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unsigned Reserved : 26;
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} __attribute__((packed));
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// xhci operational registers offset
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#define XHCI_OPS_USBCMD 0x00 // USB Command
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#define XHCI_OPS_USBSTS 0x04 // USB status
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#define XHCI_OPS_PAGESIZE 0x08 // Page size
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#define XHCI_OPS_DNCTRL 0x14 // Device notification control
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#define XHCI_OPS_CRCR 0x18 // Command ring control
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#define XHCI_OPS_DCBAAP 0x30 // Device context base address array pointer
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#define XHCI_OPS_CONFIG 0x38 // configuire
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#define XHCI_OPS_PRS 0x400 // Port register sets
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struct xhci_ops_usbcmd_reg_t
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{
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unsigned rs : 1; // Run/Stop
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unsigned hcrst : 1; // host controller reset
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unsigned inte : 1; // Interrupt enable
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unsigned hsee : 1; // Host system error enable
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unsigned rsvd_psvd1 : 3; // Reserved and preserved
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unsigned lhcrst : 1; // light host controller reset
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unsigned css : 1; // controller save state
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unsigned crs : 1; // controller restore state
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unsigned ewe : 1; // enable wrap event
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unsigned ue3s : 1; // enable U3 MFINDEX Stop
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unsigned spe : 1; // stopped short packet enable
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unsigned cme : 1; // CEM Enable
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unsigned rsvd_psvd2 : 18; // Reserved and preserved
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} __attribute__((packed));
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struct xhci_ops_usbsts_reg_t
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{
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unsigned HCHalted : 1;
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unsigned rsvd_psvd1 : 1; // Reserved and preserved
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unsigned hse : 1; // Host system error
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unsigned eint : 1; // event interrupt
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unsigned pcd : 1; // Port change detected
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unsigned rsvd_zerod : 3; // Reserved and Zero'd
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unsigned sss : 1; // Save State Status
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unsigned rss : 1; // restore state status
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unsigned sre : 1; // save/restore error
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unsigned cnr : 1; // controller not ready
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unsigned hce : 1; // host controller error
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unsigned rsvd_psvd2 : 19; // Reserved and Preserved
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} __attribute__((packed));
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struct xhci_ops_pagesize_reg_t
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{
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uint16_t page_size; // The actual pagesize is ((this field)<<12)
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uint16_t reserved;
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} __attribute__((packed));
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struct xhci_ops_dnctrl_reg_t
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{
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uint16_t value;
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uint16_t reserved;
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} __attribute__((packed));
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struct xhci_ops_config_reg_t
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{
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uint8_t MaxSlotsEn; // Max slots enabled
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unsigned u3e : 1; // U3 Entry Enable
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unsigned cie : 1; // Configuration information enable
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unsigned rsvd_psvd : 22; // Reserved and Preserved
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} __attribute__((packed));
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// xhci Extended Capabilities List ID
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// ID 部分的含义定义
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#define XHCI_XECP_ID_RESERVED 0
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#define XHCI_XECP_ID_LEGACY 1 // USB Legacy Support
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#define XHCI_XECP_ID_PROTOCAL 2 // Supported protocal
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#define XHCI_XECP_ID_POWER 3 // Extended power management
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#define XHCI_XECP_ID_IOVIRT 4 // I/0 virtualization
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#define XHCI_XECP_ID_MSG 5 // Message interrupt
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#define XHCI_XECP_ID_LOCAL_MEM 6 // local memory
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#define XHCI_XECP_ID_DEBUG 10 // USB Debug capability
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#define XHCI_XECP_ID_EXTMSG 17 // Extended message interrupt
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#define XHCI_XECP_LEGACY_TIMEOUT 10 // 设置legacy状态的等待时间
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#define XHCI_XECP_LEGACY_BIOS_OWNED (1 << 16) // 当bios控制着该hc时，该位被置位
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#define XHCI_XECP_LEGACY_OS_OWNED (1 << 24) // 当系统控制着该hc时，该位被置位
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#define XHCI_XECP_LEGACY_OWNING_MASK (XHCI_XECP_LEGACY_BIOS_OWNED | XHCI_XECP_LEGACY_OS_OWNED)
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/**
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* @brief xhci端口信息
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*
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*/
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struct xhci_port_info_t
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{
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uint8_t flags; // port flags
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uint8_t paired_port_num; // 与当前端口所配对的另一个端口（相同物理接口的不同速度的port）
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uint8_t offset; // offset of this port within this protocal
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uint8_t reserved;
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} __attribute__((packed));
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struct xhci_host_controller_t
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{
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struct pci_device_structure_general_device_t *pci_dev_hdr; // 指向pci header结构体的指针
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int controller_id; // 操作系统给controller的编号
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uint64_t vbase; // 虚拟地址base（bar0映射到的虚拟地址）
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uint64_t vbase_op; // Operational registers 起始虚拟地址
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uint32_t rts_offset; // Runtime Register Space offset
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uint32_t db_offset; // Doorbell offset
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uint32_t ext_caps_off; // 扩展能力寄存器偏移量
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uint8_t context_size; // 上下文大小
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uint16_t port_num; // 总的端口数量
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uint8_t port_num_u2; // usb 2.0端口数量
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uint8_t port_num_u3; // usb 3端口数量
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struct xhci_port_info_t ports[XHCI_MAX_ROOT_HUB_PORTS]; // 指向端口信息数组的指针
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};
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/**
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* @brief 初始化xhci控制器
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*
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* @param header 指定控制器的pci device头部
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*/
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void xhci_init(struct pci_device_structure_general_device_t *header); |