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Add in_interrupt
and refactor line discipline
This commit is contained in:
committed by
Tate, Hongliang Tian
parent
e0d7b140ce
commit
22c2cebdec
@ -1,6 +1,8 @@
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// SPDX-License-Identifier: MPL-2.0
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use crate::{arch::irq::IRQ_LIST, cpu::CpuException};
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use core::sync::atomic::{AtomicBool, Ordering};
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use crate::{arch::irq::IRQ_LIST, cpu::CpuException, cpu_local};
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#[cfg(feature = "intel_tdx")]
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use crate::arch::tdx_guest::{handle_virtual_exception, TdxTrapFrame};
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@ -71,6 +73,12 @@ extern "sysv64" fn trap_handler(f: &mut TrapFrame) {
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}
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pub(crate) fn call_irq_callback_functions(trap_frame: &TrapFrame) {
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// For x86 CPUs, interrupts are not re-entrant. Local interrupts will be disabled when
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// an interrupt handler is called (Unless interrupts are re-enabled in an interrupt handler).
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//
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// FIXME: For arch that supports re-entrant interrupts, we may need to record nested level here.
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IN_INTERRUPT_CONTEXT.store(true, Ordering::Release);
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let irq_line = IRQ_LIST.get().unwrap().get(trap_frame.trap_num).unwrap();
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let callback_functions = irq_line.callback_list();
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for callback_function in callback_functions.iter() {
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@ -79,4 +87,18 @@ pub(crate) fn call_irq_callback_functions(trap_frame: &TrapFrame) {
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if !CpuException::is_cpu_exception(trap_frame.trap_num as u16) {
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crate::arch::interrupts_ack();
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}
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IN_INTERRUPT_CONTEXT.store(false, Ordering::Release);
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}
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cpu_local! {
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static IN_INTERRUPT_CONTEXT: AtomicBool = AtomicBool::new(false);
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}
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/// Returns whether we are in the interrupt context.
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///
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/// FIXME: Here only hardware irq is taken into account. According to linux implementation, if
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/// we are in softirq context, or bottom half is disabled, this function also returns true.
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pub fn in_interrupt_context() -> bool {
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IN_INTERRUPT_CONTEXT.load(Ordering::Acquire)
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}
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