Samuka007/asterinas
1
0
Fork 0
mirror of https://github.com/asterinas/asterinas.git synced 2025-06-28 03:43:23 +00:00
Code Issues Packages Projects Releases Wiki Activity

Make ostd::trap::irq public

Browse Source
This commit is contained in:
Ruihan Li
2025-04-16 20:27:14 +08:00
committed by Tate, Hongliang Tian
parent 751e0b2ebf
commit b96c8f9ed2
45 changed files with 75 additions and 67 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
kernel/comps/virtio/src/transport/mmio/bus/common_device.rs
View File

@ -7,8 +7,8 @@ use log::info;
#[cfg(target_arch = "x86_64")]
use ostd::arch::kernel::MappedIrqLine;
#[cfg(target_arch = "riscv64")] // TODO: Add `MappedIrqLine` support for RISC-V.
use ostd::trap::IrqLine as MappedIrqLine;
use ostd::{io::IoMem, mm::VmIoOnce, trap::IrqLine, Error, Result};
use ostd::trap::irq::IrqLine as MappedIrqLine;
use ostd::{io::IoMem, mm::VmIoOnce, trap::irq::IrqLine, Error, Result};
/// A MMIO common device.
#[derive(Debug)]

2
kernel/comps/virtio/src/transport/mmio/bus/mod.rs
View File

@ -28,7 +28,7 @@ pub(super) fn init() {
fn x86_probe() {
use common_device::{mmio_check_magic, mmio_read_device_id, MmioCommonDevice};
use log::debug;
use ostd::{arch::kernel::IRQ_CHIP, io::IoMem, trap::IrqLine};
use ostd::{arch::kernel::IRQ_CHIP, io::IoMem, trap::irq::IrqLine};
// TODO: The correct method for detecting VirtIO-MMIO devices on x86_64 systems is to parse the
// kernel command line if ACPI tables are absent [1], or the ACPI SSDT if ACPI tables are

2
kernel/comps/virtio/src/transport/mmio/device.rs
View File

@ -11,7 +11,7 @@ use ostd::{
io::IoMem,
mm::{DmaCoherent, PAGE_SIZE},
sync::RwLock,
trap::IrqCallbackFunction,
trap::irq::IrqCallbackFunction,
};
use super::{

5
kernel/comps/virtio/src/transport/mmio/multiplex.rs
View File

@ -8,7 +8,10 @@ use aster_util::safe_ptr::SafePtr;
use ostd::{
io::IoMem,
sync::RwLock,
trap::{IrqCallbackFunction, IrqLine, TrapFrame},
trap::{
irq::{IrqCallbackFunction, IrqLine},
TrapFrame,
},
};
/// Multiplexing Irqs. The two interrupt types (configuration space change and queue interrupt)

2
kernel/comps/virtio/src/transport/mod.rs
View File

@ -9,7 +9,7 @@ use ostd::{
bus::pci::cfg_space::Bar,
io::IoMem,
mm::{DmaCoherent, PodOnce},
trap::IrqCallbackFunction,
trap::irq::IrqCallbackFunction,
Pod,
};

2
kernel/comps/virtio/src/transport/pci/device.rs
View File

@ -15,7 +15,7 @@ use ostd::{
},
io::IoMem,
mm::DmaCoherent,
trap::IrqCallbackFunction,
trap::irq::IrqCallbackFunction,
};
use super::{common_cfg::VirtioPciCommonCfg, msix::VirtioMsixManager};

2
kernel/comps/virtio/src/transport/pci/legacy.rs
View File

@ -12,7 +12,7 @@ use ostd::{
},
io::IoMem,
mm::{DmaCoherent, HasDaddr, PAGE_SIZE},
trap::IrqCallbackFunction,
trap::irq::IrqCallbackFunction,
};
use crate::{

4
kernel/comps/virtio/src/transport/pci/msix.rs
View File

@ -2,7 +2,7 @@
use alloc::vec::Vec;
use ostd::{bus::pci::capability::msix::CapabilityMsixData, trap::IrqLine};
use ostd::{bus::pci::capability::msix::CapabilityMsixData, trap::irq::IrqLine};
pub struct VirtioMsixManager {
config_msix_vector: u16,
@ -20,7 +20,7 @@ impl VirtioMsixManager {
pub fn new(mut msix: CapabilityMsixData) -> Self {
let mut msix_vector_list: Vec<u16> = (0..msix.table_size()).collect();
for i in msix_vector_list.iter() {
let irq = ostd::trap::IrqLine::alloc().unwrap();
let irq = IrqLine::alloc().unwrap();
msix.set_interrupt_vector(irq, *i);
}
let config_msix_vector = msix_vector_list.pop().unwrap();