Samuka007/asterinas
1
0
Fork 0
mirror of https://github.com/asterinas/asterinas.git synced 2025-06-27 19:33:23 +00:00
Code Issues Packages Projects Releases Wiki Activity

Add missing TLB flushes for coherent DMA mappings

Browse Source
This commit is contained in:
Zhang Junyang
2024-06-27 08:45:09 +00:00
committed by Tate, Hongliang Tian
parent 8cd8cf3938
commit ece62cf806
1 changed files with 3 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
ostd/src/mm/dma/dma_coherent.rs
View File

@ -10,7 +10,7 @@ use super::{check_and_insert_dma_mapping, remove_dma_mapping, DmaError, HasDaddr
#[cfg(feature = "intel_tdx")]
use crate::arch::tdx_guest;
use crate::{
arch::iommu,
arch::{iommu, mm::tlb_flush_addr_range},
mm::{
dma::{dma_type, Daddr, DmaType},
kspace::{paddr_to_vaddr, KERNEL_PAGE_TABLE},
@ -65,6 +65,7 @@ impl DmaCoherent {
.protect(&va_range, |p| p.cache = CachePolicy::Uncacheable)
.unwrap();
}
tlb_flush_addr_range(&va_range);
}
let start_daddr = match dma_type() {
DmaType::Direct => {
@ -152,6 +153,7 @@ impl Drop for DmaCoherentInner {
.protect(&va_range, |p| p.cache = CachePolicy::Writeback)
.unwrap();
}
tlb_flush_addr_range(&va_range);
}
remove_dma_mapping(start_paddr, frame_count);
}