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Add missing TLB flushes for coherent DMA mappings

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This commit is contained in:
Zhang Junyang
2024-06-27 08:45:09 +00:00
committed by Tate, Hongliang Tian
parent 8cd8cf3938
commit ece62cf806
1 changed files with 3 additions and 1 deletions
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4
ostd/src/mm/dma/dma_coherent.rs
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@ -10,7 +10,7 @@ use super::{check_and_insert_dma_mapping, remove_dma_mapping, DmaError, HasDaddr
#[cfg(feature = "intel_tdx")] #[cfg(feature = "intel_tdx")]
use crate::arch::tdx_guest; use crate::arch::tdx_guest;
use crate::{ use crate::{
arch::iommu, arch::{iommu, mm::tlb_flush_addr_range},
mm::{ mm::{
dma::{dma_type, Daddr, DmaType}, dma::{dma_type, Daddr, DmaType},
kspace::{paddr_to_vaddr, KERNEL_PAGE_TABLE}, kspace::{paddr_to_vaddr, KERNEL_PAGE_TABLE},
@ -65,6 +65,7 @@ impl DmaCoherent {
.protect(&va_range, |p| p.cache = CachePolicy::Uncacheable) .protect(&va_range, |p| p.cache = CachePolicy::Uncacheable)
.unwrap(); .unwrap();
} }
tlb_flush_addr_range(&va_range);
} }
let start_daddr = match dma_type() { let start_daddr = match dma_type() {
DmaType::Direct => { DmaType::Direct => {
@ -152,6 +153,7 @@ impl Drop for DmaCoherentInner {
.protect(&va_range, |p| p.cache = CachePolicy::Writeback) .protect(&va_range, |p| p.cache = CachePolicy::Writeback)
.unwrap(); .unwrap();
} }
tlb_flush_addr_range(&va_range);
} }
remove_dma_mapping(start_paddr, frame_count); remove_dma_mapping(start_paddr, frame_count);
} }