11 Commits

Author	SHA1	Message	Date
Zejun Zhao	bd24ed9ba7	Support RISC-V ISA extension detection	2025-06-11 16:54:59 +08:00
Zejun Zhao	ffb4097436	Add RISC-V timer support	2025-05-29 19:51:02 +08:00
Ruihan Li	758c80c321	Pull code from arch/*/irq.rs to trap/irq.rs	2025-05-25 10:19:17 +08:00
Ruihan Li	8c30b4b942	Rewrite trap/gdt.rs	2025-04-22 20:52:15 +08:00
Ruihan Li	e06509e380	Make some unsafe blocks shorter	2025-04-22 20:52:15 +08:00
Zejun Zhao	5630fa8b36	Disable RISC-V FPU by default	2025-04-18 13:26:16 +08:00
Zejun Zhao	14b8c48859	Adjust RISC-V's implementation for recent changes	2025-04-18 13:26:16 +08:00
Ruihan Li	b52d841ac1	Revise safety comments for booting APs	2025-04-03 10:50:22 +08:00
Yuke Peng	322fc4feff	Refactor PCI access in OSTD	2025-03-29 09:16:40 +08:00
Zhang Junyang	92bc8cbbf7	Make CPU-local and early ACPI initialization heap-less	2025-03-14 08:37:37 +08:00
YanWQ-monad	4fa0e6334b	Add RISC-V base support	2024-09-30 10:02:08 +08:00