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71 lines
1.8 KiB
Rust
71 lines
1.8 KiB
Rust
// SPDX-License-Identifier: MPL-2.0
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//! Platform-specific code for the RISC-V platform.
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pub mod boot;
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pub(crate) mod cpu;
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pub mod device;
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pub mod iommu;
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pub(crate) mod irq;
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pub(crate) mod mm;
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pub(crate) mod pci;
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pub mod qemu;
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pub mod serial;
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pub mod task;
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pub mod timer;
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pub mod trap;
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#[cfg(feature = "cvm_guest")]
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pub(crate) fn init_cvm_guest() {
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// Unimplemented, no-op
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}
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pub(crate) unsafe fn late_init_on_bsp() {
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// SAFETY: This function is called in the boot context of the BSP.
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unsafe { trap::init() };
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// SAFETY: We're on the BSP and we're ready to boot all APs.
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unsafe { crate::boot::smp::boot_all_aps() };
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// SAFETY: This function is called once and at most once at a proper timing
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// in the boot context of the BSP, with no timer-related operations having
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// been performed.
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unsafe { timer::init() };
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let _ = pci::init();
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}
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pub(crate) unsafe fn init_on_ap() {
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unimplemented!()
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}
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pub(crate) fn interrupts_ack(irq_number: usize) {
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unimplemented!()
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}
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/// Return the frequency of TSC. The unit is Hz.
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pub fn tsc_freq() -> u64 {
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timer::get_timebase_freq()
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}
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/// Reads the current value of the processor’s time-stamp counter (TSC).
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pub fn read_tsc() -> u64 {
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riscv::register::time::read64()
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}
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/// Reads a hardware generated 64-bit random value.
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///
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/// Returns None if no random value was generated.
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pub fn read_random() -> Option<u64> {
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// FIXME: Implement a hardware random number generator on RISC-V platforms.
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None
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}
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pub(crate) fn enable_cpu_features() {
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cpu::extension::init();
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unsafe {
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// We adopt a lazy approach to enable the floating-point unit; it's not
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// enabled before the first FPU trap.
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riscv::register::sstatus::set_fs(riscv::register::sstatus::FS::Off);
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}
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}
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