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Fix the detection of RISC-V SSTC extension

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This commit is contained in:
Zejun Zhao
2025-06-03 00:52:39 +08:00
committed by Tate, Hongliang Tian
parent bd24ed9ba7
commit 492898d1d5
1 changed files with 3 additions and 6 deletions
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9
ostd/src/arch/riscv/timer/mod.rs
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@ -8,8 +8,8 @@ use core::{
}; };
use crate::{ use crate::{
arch::boot::DEVICE_TREE, arch::{self, boot::DEVICE_TREE},
cpu::{CpuId, PinCurrentCpu}, cpu::{CpuId, IsaExtensions, PinCurrentCpu},
timer::INTERRUPT_CALLBACKS, timer::INTERRUPT_CALLBACKS,
trap, trap,
}; };
@ -107,10 +107,7 @@ fn set_next_timer_sstc() {
} }
fn is_sstc_enabled() -> bool { fn is_sstc_enabled() -> bool {
let Some(misa) = riscv::register::misa::read() else { arch::cpu::has_extensions(IsaExtensions::SSTC)
return false;
};
misa.has_extension('S')
} }
fn get_next_when() -> u64 { fn get_next_when() -> u64 {