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Support RISC-V ISA extension detection

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This commit is contained in:
Zejun Zhao
2025-06-03 00:43:33 +08:00
committed by Tate, Hongliang Tian
parent 0ddc1bb2d2
commit bd24ed9ba7
3 changed files with 375 additions and 0 deletions
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1
ostd/src/arch/riscv/mod.rs
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@ -61,6 +61,7 @@ pub fn read_random() -> Option<u64> {
}
pub(crate) fn enable_cpu_features() {
cpu::extension::init();
unsafe {
// We adopt a lazy approach to enable the floating-point unit; it's not
// enabled before the first FPU trap.